Semiconductor circuit having improved layout pattern

A semiconductor circuit comprising:

• a plurality of first power supply lines which are arranged in parallel to each other and supplying a power supply voltage;
• a plurality of second power supply lines which are arranged in parallel to each other and supply a power supply voltage different from that supplied by said first power supply lines, said first and second power supply lines running in parallel to each other in a first direction;
• a first cell made up of the same number of first p-channel transistors and first n-channel transistors which are respectively coupled to said first and second power supply lines, said first p-channel transistors and said first n-channel transistors being alternately arranged in a second direction and having the same size;
• and
• a second cell made up of a first number of second p-channel transistors and a second number of second n-channel transistors which are respectively coupled to said first and second power supply lines, said second p-channel transistors and said second n-channel transistors being alternately arranged in said second direction, said first number and said second number being different;
• said second p-channel transistors being electrically coupled in parallel, so that said second p-channel transistors have a predetermined driving capability.