Semiconductor device
AssigneeSeiko Instruments Inc.
InventorsKoju Nonaka, Shigeyuki Tsunoda, Kenji Kitamura
Life of this patent
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Abstract
The semiconductor device contains a CMOS transistor pair comprised of a P channel MOS transistor having a polysilicon gate 4 and an N channel MOS transistor having a polysilicon gate. The MOS transistor has a channel dope layer 5 localized in a vicinity of a surface of a channel region just below a gate electrode. This channel dope layer 5 has a quite shallow p-n junction depth xj effective to suppress a leak current. Thereby, an amount of impurity concentration in the surface of the channel region can be reduced to improve a subthreshold characteristics of the MOS transistor and to enable a low voltage and high speed operation under suppressing a leakage current.
Claims22
A semiconductor device containing a CMOS transistor pair, comprising:
- a P channel MOS transistor and an N channel MOS transistor each formed in a semiconductor substrate, the P channel MOS transistor comprising a pair of source and drain regions formed in spaced relation from each other in the semiconductor substrate, a channel dope layer formed locally in a vicinity of a surface of the semiconductor substrate between the pair of source and drain regions, a gate insulating film formed on the semiconductor substrate over the channel dope layer, and a polysilicon gate formed on the gate insulating film, wherein the channel dope layer has a p-n junction depth of about or less than 0.2 .mu.m from the surface of the semiconductor substrate effective to suppress a leak current between the source and drain regions such that the P channel MOS transistor has a subthreshold coefficient S of less than 85 mV/decade.
A microcomputer having a single chip containing a CMOS transistor pair, comprising:
- a P channel MOS transistor having a polysilicon gate and an N channel MOS transistor having a polysilicon gate, the P channel MOS transistor comprising a pair of source and drain regions formed in spaced relation from each other in an N type semiconductor layer formed in a semiconductor substrate, a channel dope layer having P type impurities formed locally in a vicinity of a surface of the N type semiconductor layer between the pair of source and drain regions, and a gate insulating film formed on the N type semiconductor layer over the channel dope layer, wherein the channel dope layer has a depth of about or less than 0.2 .mu.m from the surface of the N type semiconductor layer such that the P channel MOS transistor has a subthreshold coefficient S of less than 85 mV/decade effective to suppress a leak current between the source and drain regions.
A semiconductor device having a CMOS transistor pair, comprising;
- a P channel MOS transistor comprising a source region and a drain region formed in an N type semiconductor layer, a channel dope layer having P type impurities formed locally in a surface of the N type semiconductor layer between the source region and the drain region, the channel dope layer having a depth effective to suppress a leak current between the source region and the drain region to a value about or less than 10.sup.-9 amps and having a P type impurity concentration effective to suppress the threshold voltage of the P channel MOS transistor to an absolute value of less than 0.6 volts.
A microcomputer according to claim 29;
- wherein the N channel MOS transistor has a threshold voltage having an absolute value of less than 0.6 volts.
Dependencies are inferred from the claim text.