Semiconductor device having an evaluation device and method of fabricating same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakuo Matsusako, Kazumasa Satsuma
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Abstract
There are provided a plurality of standard cell blocks (2) within an IC chip (1), and an aluminium wiring layer is formed in an aluminium wiring region (8) provided between the standard cell blocks (2) to electrically connect the standard cell blocks (2) to each other. An n-type epitaxial region (4), a p-type diffusion region (5) and an n-type diffusion region (6) are incorporated in an underlayer of the aluminium wiring region (8), to thereby form an evaluation device which is an npn bipolar transistor under the aluminium wiring region (8). A semiconductor device which is capable of accurately evaluating its finished product by the inspection of the evaluation device is provided without the damage of an integration level.
Claims7
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of transistor elements formed in said semiconductor substrate;
- a metal wiring layer provided in a wiring region between said plurality of transistor elements for electrically connecting said plurality of transistor elements to each other;
- an evaluation pad to be monitored formed on said semiconductor substrate independently of said metal wiring layer;
- an insulator film formed under said wiring region;
- and
- an evaluation element to be monitored formed under said wiring region and said insulator film and having an electrode region, said electrode region being capable of making electrical contact with said evaluation pad.
Dependencies are inferred from the claim text.