Back to results
US 5,489,790 AGranted
Static-random-access memory cell
AssigneeMotorola, Inc.
InventorCraig S. Lage
Life of this patent
Estimating the term…
Abstract
An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.
Claims10
A static-random-access memory cell comprising:
- a semiconductor substrate having a first conductivity type;
- a buried oxide layer overlying the substrate;
- a first doped region overlying the buried oxide layer, wherein the first doped region has a second conductivity type that is opposite the first conductivity type;
- a first semiconductor layer overlying the first doped region and having the first conductivity type;
- a trench extending through the buried oxide layer, first doped region, and first semiconductor layer, wherein:
- the trench has a wall surface, a bottom surface, and a central region;
- and
- a channel region of a first transistor lies within the first semiconductor layer adjacent to the wall surface of the trench;
- a second doped region, wherein the second doped region:
- has the second conductivity type;
- and
- lies within the first semiconductor layer and adjacent to the wall surface;
- a second semiconductor layer overlying the substrate within the central region of the trench, wherein:
- the second semiconductor layer has the second conductivity type;
- the second semiconductor layer has a wall surface that faces the wall surface of the trench;
- and
- a channel region of a second transistor lies within the second semiconductor layer and adjacent to the wall surface of the second semiconductor layer;
- a third doped region lying within the second semiconductor layer and having the first conductivity type;
- a first gate dielectric layer lying adjacent to the wall surfaces of the trench and second semiconductor layer and adjacent to the bottom of the trench outside of the central region;
- and
- a first conductive member, wherein the first conductive member:
- lies at least partially within the trench and adjacent to the first gate dielectric layer;
- laterally surrounds the second semiconductor layer;
- and
- acts as a shared-gate electrode for the first and second transistors.
22 more elements
A static-random access memory cell comprising:
- a semiconductor substrate having a first conductivity type;
- a buried oxide layer overlying the substrate;
- a first doped region overlying the buried oxide layer, wherein the first doped region has a second conductivity type that is opposite the first conductivity type;
- a first semiconductor layer overlying the first doped region and having the first conductivity type;
- a first trench and a second trench, wherein:
- the first and second trenches are spaced apart from each other;
- each of the first and second trenches extends through the buried oxide layer, first doped region, and first semiconductor layer;
- each of the first and second trenches has a wall surface, a bottom surface, and a central region;
- a channel region of a first latch transistor lies within the first semiconductor layer adjacent to the wall surface of the first trench;
- and
- a channel region of a second latch transistor lies within the first semiconductor layer adjacent to the wall surface of the second trench;
- a second doped region and a third doped region, wherein:
- the second doped region:
- has the second conductivity type;
- and
- lies within the first semiconductor layer and adjacent the wall surface of the first trench;
- and
- the third doped region:
- has the second conductivity type;
- and
- lies within the first semiconductor layer and adjacent the wall surface of the second trench;
- and
- is spaced apart from the second doped region;
- a second semiconductor layer overlying the substrate within the central region of each of the trenches, wherein:
- the second semiconductor layer has the second conductivity type;
- a first portion of the second semiconductor layer lies within the first trench and has a wall surface that faces the wall surface of the first trench;
- a channel region of a first load transistor lies adjacent to the wall surface of the first portion;
- a second portion of the second semiconductor layer lies within the second trench and has a wall surface that faces the wall surface of the second trench;
- and
- a channel region of a second load transistor lies adjacent to the wall surface of the second portion;
- a fourth doped region lying within a part of the first portion of the second semiconductor layer, wherein the fourth doped region has the first conductivity type;
- a fifth doped region lying within that a part of the second portion of the second semiconductor layer, wherein the fifth doped region has the first conductivity type;
- a first gate dielectric layer lying adjacent to the wall surfaces of the first trench and the first portion of the second semiconductor layer and adjacent to the bottom of the first trench outside of the central region of the first trench;
- a second gate dielectric layer lying adjacent to the wall surfaces of the second trench and the second portion of the second semiconductor layer and adjacent to the bottom of the second trench outside of the central region of the second trench;
- a first conductive member, wherein:
- the first conductive member lies at least partially within the first trench and adjacent to the first gate dielectric layer;
- the first conductive member laterally surrounds the first portion of the second semiconductor layer;
- and
- the first conductive member acts as a shared-gate electrode for the first latch and first load transistors;
- a second conductive member, wherein:
- the second conductive member lies at least partially within the second trench and adjacent to the second gate dielectric layer;
- the second conductive member laterally surrounds the second portion of the second semiconductor layer;
- and
- the second conductive member acts as a shared-gate electrode for the second latch and second load transistors;
- a sixth doped region having the second conductivity type, wherein the sixth doped region:
- lies within the first semiconductor layer;
- and is spaced apart from the second and third dopant regions;
- a seventh doped region having the second conductivity type, wherein the seventh doped region:
- lies within the first semiconductor layer;
- and is spaced apart from the second, third, and sixth doped regions;
- and
- a third conductive member, wherein the third conductive member:
- overlies portions of the second, third, sixth, and seventh doped regions, a portion of the first semiconductor layer that lies between the second and sixth doped regions, and another portion of the first semiconductor layer that lies between the third and seventh doped regions;
- and
- acts as gate electrodes for access transistors of the memory cell.
52 more elements
Dependencies are inferred from the claim text.