US 5,489,546 AGranted

Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process

AssigneeMicron Technology, Inc.

InventorsAftab Ahmad, Pierre C. Fazan, Charles H. Dennison

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Abstract

NMOS and PMOS devices are formed in a split-polysilicon CMOS process using independent thickness transistor gate spacers, and using a silicon nitride layer as a mask for the p-channel region during an n+ source/drain implant step of the n-channel region. The p-channel spacer is formed significantly thicker than the n-channel spacer, thereby reducing lateral diffusion of p-type dopant species under the p-channel gate and avoiding short channel effects to improve device reliability and performance. P-channel transistor junction depth and lateral diffusion is further reduced by performing an n-channel arsenic source/drain implant before the p-channel source/drain boron difluoride implant, although the p-channel transistor gate is etched before the n-channel gate. Moreover, since the p-channel transistor gate is etched before the n-channel gate, the p-channel gate sidewalls are reoxidized as well as the n-channel gate sidewalls for improved gate oxide integrity.

Claims16

Dependent claims

A process for forming complementary n-channel and p-channel CMOS devices on a semiconductor wafer substrate having conductive and non conductive layers of transistor gate materials over n-channel and p-channel regions, and having a first insulating layer as a top layer, the process comprising:

(a) forming a p-channel gate structure in the layers of gate materials in the p-channel region;
(b) depositing a second insulating layer over all exposed surfaces, whereby foundational walls for a p-channel spacer are formed adjacent to and on either side of the p-channel gate structure in future active areas of the p-channel region;
(c) masking the p-channel region and forming an n-channel gate structure in the n-channel region;
(d) removing the mask and then depositing a third insulating layer, whereby foundational walls for an n-channel spacer are formed adjacent to and on either side of the n-channel gate structure in future active areas of the n-channel region, and whereby the third insulating layer adds to the p-channel spacer foundational walls to form a thicker overall p-channel spacer in the future active areas of the p-channel region, the thicker spacer being thicker relative to the n-channel spacer;
(e) etching the third insulating layer to the substrate in the future active areas of the n-channel region to form the n-channel spacer adjacent to and on either side of the n-channel gate in the n-channel future active areas, and whereby a part of the second insulating layer remains unetched in the p-channel region over the future p-channel active areas;
(f) implanting n-type ions in the n-channel future active areas to form source and drain areas;
(g) masking the n-channel region and then etching, whereby the part of the second insulating layer in the p-channel future active areas is etched to the substrate in a region defined by the thicker overall p-channel spacer;
and,
(h) implanting p-type ions in the p-channel future active areas to form source and drain areas defined by the thicker overall p-channel spacer, whereby the source and drain areas have reduced lateral diffusion for avoiding short channel effects.

6 more elements

A process for forming complementary n-channel and p-channel metal oxide semiconductor (CMOS) devices on a semiconductor wafer substrate having conductive and non conductive layers of transistor gate materials over n-channel and p-channel regions, the process comprising:

(a) depositing a first insulating layer over all exposed surfaces in the n-channel and p-channel regions;
(b) patterning with a first photoresist layer and then etching a p-channel gate having sidewalls, and source and drain areas in the p-channel region;
(c) forming an n-type diffusion in the p-channel source and drain areas;
(d) stripping the first photoresist layer;
(e) reoxidizing the p-channel gate sidewalls and source and drain areas;
(f) depositing a second insulating layer over all exposed surfaces in the n-channel and p-channel regions, whereby a foundation for a first p-channel spacer is formed adjacent to and on either side of the p-channel gate, and an insulating layer is formed in the p-channel source and drain areas for acting as a mask for a later step;
(g) patterning with a second photoresist layer whereby the p-channel region is masked, and then etching an n-channel gate having sidewalls, and source and drain areas in the n-channel region;
(h) forming a p-type diffusion and then an n-type diffusion over the p-type diffusion in the n-channel source and drain areas;
(i) stripping the second photoresist layer;
(j) reoxidizing the n-channel gate sidewalls and source and drain areas;
(k) depositing a third insulating layer over all exposed surfaces in the n-channel and p-channel regions;
(l) etching the third insulating layer to the substrate in the n-channel region to form a first n-channel spacer adjacent to and on either side of the n-channel gate, and a second p-channel spacer is formed adjacent the first p-channel spacer thereby forming in connection with the first p-channel spacer a thicker overall p-channel spacer than the first n-channel spacer, and whereby a part of the second insulating layer acting as the mask over the p-channel source and drain areas is not substantially etched;
(m) implanting n-type ions in the n-channel source and drain areas, thereby forming an n-channel source and drain;
(n) masking the n-channel region and etching, whereby the part of the second insulating layer in the p-channel source and drain areas that is acting as a mask is etched to the substrate in a region defined by the thicker overall p-channel spacer;
and,
(o) implanting p-type ions in the p-channel source and drain areas defined by the thicker overall p-channel spacer, thereby forming a p-channel source and drain having reduced lateral diffusion to avoid short channel effects.

13 more elements

Dependencies are inferred from the claim text.