US 5,489,540 A · Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask

Abstract

A novel CMOS fabrication process that eliminates several masks of a conventional process by delaying application of a well mask to a semiconductor structure until after formation of isolation regions and gate structures. Providing for three separate implant steps and selectively implanting dopants through an exposure window of the well mask, through gate structures, and through the well mask allows formation of the well region, and source/drain regions in the well region, and in the region covered by the well mask. When LDD implants are desired, removal of a lateral spacer on the gate overlying the well region and subsequent LDD implant through the mask region introduces the LDD implant. Separate masks for source/drain regions and LDD regions are not required. In an alternate embodiment, the LDD implant is introduced prior to formation of lateral spacers on gate structures and application of the well mask, providing the LDD implant in both channels, and eliminating a requirement for lateral spacer removal.

Claims11

Dependent claims

A method for forming a complementary metal oxide semiconductor (CMOS) structure, comprising the steps of:

forming, in a substrate, a first active region and an second active region separated from said first active region by an isolation region;
thereafter
forming a first gate overlying a portion of said first active region;
and
forming a second gate overlying a portion of said second active region;
and thereafter
masking said first active region with a well mask having an exposure window to expose said second active region and a portion of said isolation region;
thereafter
implanting dopants of a first conductivity type through said exposure window and said second gate into said substrate to create a well region of said first conductivity type, said well region having a depth contour;
implanting dopants of a second conductivity type through said exposure window to form a source region and a drain region in said second active region that are each latterly disposed away from said gate in said second active region;
and
implanting dopants of said first conductivity type through said exposure window to shape said depth contour and through said well mask to form a source region and a drain region in said first active region that are each latterly disposed away from said gate in said first active region.

9 more elements

Dependencies are inferred from the claim text.

Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask

Life of this patent

Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask

Life of this patent

Abstract

Claims11