Method and circuitry for clock synchronization

A method of performing phase adjustment in a phase locked loop to generate a first output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, comprising the steps of:

• a) selecting a first even phase signal from the multiplicity of even phase signals in response to an even select signal;
• b) selecting a first odd phase signal from the multiplicity of odd phase signals in response to an odd select signal, wherein each of the even and odd select signals is generated in response to a control signal;
• c) generating an even weighting signal and an odd weighting signal in response to the control signal, wherein the control signal causes the even and odd weighting signals to control interpolation between the first even and first odd phase signals when one of the first even and odd select signals is changing states;
• and
• d) interpolating between the first even phase signal and the first odd phase signal to generate the first output phase signal in response to the even weighting signal and the odd weighting signal, the even weighting signal preventing the first even phase signal from contributing to the first output phase signal when the even select signal is changing states, and the odd weighting signal preventing the first odd phase signal from contributing to the first output phase signal when the odd select signal is changing states.

Phase tuning circuitry for generating an output phase signal from a multiplicity of input phase signals, comprising:

• a) a select circuit for generating a select signal in response to a control signal;
• b) a weighting circuit for generating a weighting signal in response to the control signal;
• c) a phase selector for selecting a first phase signal and a second phase signal from the multiplicity of input phase signals in response to the select signal;
• and
• d) a phase interpolator for interpolating between the first phase signal and the second phase signal to generate the output phase signal in response to the weighting signal, wherein the weighting signal is used to control interpolation between the first and second phase signals when the select signal is changing states, wherein the select signal and the weighting signal are generated in response to the control signal.

Phase tuning circuitry for generating an output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, the phase tuning circuitry comprising:

• a) a select signal generator for generating an even select signal and an odd select signal in response to a control signal;
• b) a weighting signal generator for generating an even weighting signal and an odd weighting signal in response to the control signal;
• c) a phase selector for selecting an even phase signal from the multiplicity of even phase signals in response to an even select signal and for selecting an odd phase signal from the multiplicity of odd phase signals in response to an odd select signal;
• and
• d) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal in response to the even weighting signal and the odd weighting signal, wherein the control signal causes the even and odd weighting signals to control interpolation between the even and odd phase signals when one of the even and odd select signals is changing states, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, and the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states.

Phase tuning circuitry for generating an output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, the phase tuning circuitry having fast power up and power down response characteristics, the phase tuning circuitry comprising:

• a) a select signal generator for generating an even select signal and an odd select signal in response to a control signal;
• b) a weighting signal generator for generating an even weighting signal and an odd weighting signal in response to the control signal;
• c) a phase selector for selecting an even phase signal from the multiplicity of even phase signals in response to the even select signal and for selecting an odd phase signal from the multiplicity of odd phase signals in response to the odd select signal;
• and
• d) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal in response to the even weighting signal and the odd weighting signal wherein the control signal causes the even and odd weighting signals to control interpolation between the even and odd phase signals when one of the even and odd select signals is changing states, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, and the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states.

Phase tuning circuitry for generating an output phase signal, comprising:

• a) an accumulator for generating an underflow/overflow signal and a count signal in response to a control signal;
• b) a digital to analog converter for generating an even weighting signal and an odd weighting signal in response to the count signal;
• c) control circuitry for generating a barrel shift control signal in response to the underflow/overflow signal;
• d) a first barrel shifter generating a multiplicity of even select signals in response to the barrel shift control signal;
• and
• e) a second barrel shifter generating a multiplicity of odd select signals in response to the barrel shift control signal;
• f) a phase selector comprising:
• i) a first multiplexing means for selecting an even phase signal from a multiplicity of even phase signals in response to the multiplicity of even select signals;
• ii) a second multiplexing means for selecting an odd phase signal from a multiplicity of odd phase signals in response to the multiplicity of odd select signals;
• and
• g) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal, the phase interpolator comprising:
• i) a first differential amplifier coupled to the even phase signal and the even weighting signal, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, the first differential amplifier having a first output;
• and
• ii) a second differential amplifier coupled to the odd phase signal and the odd weighting signal, the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states, the second differential amplifier having a second output coupled to the first output.