MOS electrostatic discharge protection device and structure
AssigneeIntegrated Device Technology, Inc.
InventorChuen-Der Lien
Life of this patent
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Abstract
A PMOS transistor is coupled directly to both V.sub.CC and V.sub.SS, for use in an electrostatic discharge (ESD) protection device, thereby protecting the I/O pad(s) of an integrated circuit. The direct coupling of the PMOS transistor to both voltage levels, V.sub.CC and V.sub.SS, greatly reduces the overall ESD hazard, i.e, to all four ESD conditions: 1) positive against V.sub.SS, 2) negative against V.sub.SS, 3) positive against V.sub.CC, and 4) negative against V.sub.CC, the most critical of these tests being the positive against V.sub.SS and positive against V.sub.CC.
Claims3
An electrostatic discharge protection structure for an I/O pad of an integrated circuit having a semiconductor substrate, said structure comprising:
- a first terminal to permit application thereto of a first supply voltage;
- a second terminal to permit application thereto of a second supply voltage;
- and
- a PMOS transistor having a drain coupled to said first terminal, a source coupled directly to the I/O pad, and a gate coupled to an output node of an inverter whose input node is coupled to said first terminal, wherein said PMOS transistor is disposed within an N region and said N-region is coupled to said second terminal.
Dependencies are inferred from the claim text.