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US 5,479,034 AGranted
Method of making gate array base cell
AssigneeTexas Instruments Incorporated
InventorsMashashi Hashimoto, Shivaling S. Mahant-Shetti
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Abstract
A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.
Claims36
A base cell within an array of base cells, each of said base cells comprising:
- a moat region of a first conductivity type formed in a semiconductor substrate;
- a continuous channel region of a second conductivity type, said second conductivity type different than said first conductivity type, said channel region separating said moat region into at least three separate source/drain regions wherein the extent of the junction between said channel region and said first source/drain region is larger than the extent of the junction between said channel region and said second source/drain region:
- an insulating layer formed above said channel region;
- and
- a gate formed above said insulating layer;
- wherein said region of first conductivity type in about half of said base cells comprises n doped silicon and wherein said region of first conductivity type in the remaining base cells comprises p doped silicon.
3 more elements
A semiconductor structure comprising:
- an active area formed in the face of a semiconductor workpiece;
- at least three separate source/drain regions in said active area, said at least three source/drain regions separated by a continuous channel region wherein said at least three source/drain regions comprise a first source/drain region, a second source/drain region, and a third source/drain region wherein said first source/drain region is larger than said second source/drain region and wherein said second source/drain region is larger than said third source/drain region;
- and
- a conductive gate insulatively overlying said channel region.
1 more element
An array of base cells, each of said cells comprising:
- a substantially rectangular region of a first conductivity type formed in a semiconductor substrate;
- a continuous channel region of a second conductivity type, said second conductivity type different than said first conductivity type, said channel region separating said moat region into exactly three separate source/drain regions;
- an insulating layer formed above said channel region;
- and
- a gate formed above said insulating layer;
- and
- an insulating region formed between said base cells.
4 more elements
A base cell within an array of base cells, said base cell comprising:
- a substantially rectangular moat region of a first conductivity type formed in a semiconductor substrate;
- a continuous channel region of a second conductivity type, said second conductivity type different than said first conductivity type, said channel region separating said moat region into at least three separate source/drain regions wherein the extent of the junction between said channel region and said first source/drain region is larger than the extent of the junction between said channel region and said second source/drain region;
- an insulating layer formed above said channel region;
- and
- a gate formed above said insulating layer.
2 more elements
A gate array base cell comprising a p-moat region including first, second, third, fourth and fifth p-regions and an n-moat region wherein:
- said first and second p-regions comprise the source and drain of a first p-channel transistor, said first p-channel transistor including a first gate;
- said first and third p-regions comprise the source and drain of a second p-channel transistor, said second p-channel transistor including said first gate;
- said first and fourth p-regions comprise the source and drain of a third p-channel transistor, said third p-channel transistor including a second gate;
- and
- said first and fifth p-regions comprise the source and drain of a fourth p-channel transistor, said fourth p-channel transistor including said second gate.
2 more elements
An array of substantially identical gate array base cells, each base cell including:
- a p-channel transistor section, said p-channel transistor section including at least three p-doped source/drain regions, said at least three p-doped source/drain regions configurable to comprise source/drain regions of at least two different size PMOS transistors;
- and
- an n-channel transistor section, said n-channel transistor section including at least two n-doped source/drain regions, said at least two n-doped source/drain regions configurable to comprise source/drain regions of an NMOS transistor.
A CMOS gate array base cell comprising:
- a p-channel transistor section comprising a first PMOS transistor which includes first and second source/drain regions separated by a first channel region, said p-channel transistor section also comprising a second PMOS transistor which includes third and fourth source/drain regions separated by a second channel region, said first and second PMOS transistors having different channel conductivities;
- and
- an n-channel transistor section comprising an NMOS transistor which includes at least two n-doped source/drain regions separated by an n-channel region.
A CMOS gate array base cell comprising:
- a first transistor section comprising a first and second transistors of a first conductivity type, said first transistor including first and second source/drain regions separated by a first channel region, and said second transistor including third and fourth source/drain regions separated by a second channel region, said first and second transistors having different channel conductivities;
- and
- a second transistor section comprising at least one transistor of a second conductivity type, said second conductivity type being different than said first conductivity type.
A semiconductor structure comprising:
- an active area formed in the face of a semiconductor workpiece;
- two continuous channel regions disposed in said active area, said two continuous channel regions dividing said active area into exactly five separate source/drain regions;
- and
- a conductive gate insulatively overlying each of said channel regions.
1 more element
A gate array base cell, comprising:
- a first pair of P-channel transistors having a first predetermined transconductance area;
- a second pair of P-channel transistors having a second predetermined transconductance area, said second predetermined transconductance area being smaller than said first predetermined transconductance area;
- and
- a first pair of N-channel transistors, a first one of said first pair of N-channel transistors having a gate coupled to a gate of a first one of said first pair of P-channel transistors and to a gate of a first one of said second pair of P-channel transistors, a second one of said first pair of N-channel transistors having a gate coupled to a gate of a second one of said first pair of P-channel transistors and to a gate of a second one of said second pair of P-channel transistors.
1 more element
Dependencies are inferred from the claim text.