Method of manufacturing a semiconductor memory device having improved hold characteristic of a storage capacitor

A method of manufacturing a semiconductor device including a plurality of memory cells, each memory cell having a transistor and a capacitor, said method comprising the steps of:

• forming said transistor on a semiconductor substrate, said transistor having source and drain regions selectively formed in said semiconductor substrate and a gate formed on a gate insulating film covering a portion of said semiconductor substrate between said source and drain regions;
• forming an interlayer insulating layer covering said semiconductor substrate having said transistor;
• forming a first polysilicon layer on said interlayer insulating layer;
• removing a portion of said first polysilicon layer without substantially etching said interlayer insulating layer in order to form a first hole in said first polysilicon layer, said first polysilicon having a sidewall surface defining said first hole and a portion of said insulating layer located over one of said source and drain regions, said one of said source and drain regions being exposed by said first hole;
• depositing a second polysilicon layer over an entire surface and etching back said second polysilicon to form a spacer in contact with said sidewall surface of said first polysilicon, said spacer further being in contact with a part of said portion of said interlayer insulating layer to define a second hole for exposing a remaining part of said portion of said interlayer insulating layer;
• selectively removing said interlayer insulating layer by using said spacer as a mask to form a third hole in said interlayer insulating layer, said third hole exposing a part of said one of said source and drain regions and having a size which is substantially the same as the size of said second hole;
• forming a third polysilicon layer which fills said second and third holes and is in contact with said spacer and said first polysilicon layer;
• patterning said first and third polysilicon layers to form a lower electrode of said capacitor;
• forming a dielectric film of said capacitor on said lower electrode;
• and
• forming an upper electrode of said capacitor on said dielectric film.

A method of manufacturing a semiconductor device including a plurality of memory cells, each of said memory cells having a transistor and a capacitor, said method comprising the steps of:

• forming said transistor in a semiconductor substrate, said transistor having source and drain regions selectively formed in said semiconductor substrate and a gate formed on a gate insulating film covering a portion of said semiconductor substrate between said source and drain regions;
• forming a first insulating layer to cover said semiconductor substrate having said transistor;
• forming a first hole in said first insulating film to expose a part of one of said source and drain regions;
• forming a bit line in contact through said first hole, said contact being with said part of said one of said source and drain regions;
• forming a second insulating film on said first insulating film and said bit line;
• forming a first polysilicon layer on said second insulating film;
• forming a second hole in said first polysilicon layer by selectively removing said first polysilicon layer without substantially etching said second insulating film, said second hole being defined by a sidewall surface of said first polysilicon layer and exposing a portion of said second insulating film located over the other of said surface and drain regions;
• forming a spacer made of polysilicon in contact with said sidewall of said first polysilicon layer, said spacer being further in contact with a part of said portion of said second insulating film and defining a third hole exposing a remaining part of said portion of said second insulating film;
• forming a fourth hole in said first and second insulating film by selectively removing said first and second insulating films by using said spacer as a mask, said fourth hole having a size which is substantially the same as the size of said third hole and exposing a part of said other of said source and drain regions;
• depositing a second polysilicon layer on said spacer and said first polysilicon layer with a resulting filling of said fourth hole;
• and
• patterning said first and second polysilicon layers to form a lower electrode of said capacitor, said first and second polysilicon layer having substantially the same pattern.