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US 5,477,501 AGranted
Semiconductor random access memory device having digit lines selectively extending on inter-level insulating layers
AssigneeNEC Corporation
InventorHisamitsu Suzuki
Life of this patent
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Abstract
A semiconductor static random access memory device has a plurality of memory cells selectively connected to digit lines, and the digit lines are formed on different inter-level insulating layers in a partially overlapped manner so as to scale down the memory cells only.
Claims9
A semiconductor memory device fabricated on a semiconductor substrate, comprising:
- a memory cell array having a plurality of memory cells formed on a surface of said semiconductor substrate for storing data information;
- a plurality of word lines selectively connected to said plurality of memory cells so as to allow an external device to selectively access said plurality of memory cells;
- a plurality of data propagation paths selectively connected to said plurality of memory cells for transferring said data information from said memory cell array;
- an interface means for communicating said external device;
- an addressing system selectively energizing said plurality of word lines for transferring said data information through said plurality of data propagation paths between said memory cell array and said interface means;
- and
- an inter-level insulating film structure covering said memory cell array and said plurality of word lines, and having a plurality of inter-level insulating layers, said plurality of data propagation paths being selectively formed on said plurality of inter-level insulating layers.
4 more elements
A semiconductor memory device fabricated on a semiconductor substrate, comprising:
- a memory cell array having a plurality of memory cells each having
- two inverters having respective input nodes and respective output nodes, the input node of each of said two inverters being connected to the output node of the other of said two inverters, and
- two access transistors having respective first transfer nodes and respective second transfer nodes respectively connected to said input nodes of said two inverters;
- a plurality of digit lines selectively connected to said first transfer nodes of the access transistors of said plurality of memory cells;
- and
- a plurality of inter-level insulating layers provided over said memory cell array and laminated on one another, adjacent digit lines of said plurality of digit lines being formed on said plurality of inter-level insulating layers.
3 more elements
Dependencies are inferred from the claim text.