US 5,477,176 AGranted

Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory

AssigneeMotorola, Inc.

InventorsRay Chang, Lawrence F. Childs, Kenneth W. Jones, Donovan Raatz, Stephen Flannagan

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Abstract

A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

Claims19

Dependent claims

An integrated circuit memory, comprising:

a plurality of memory cells organized in rows and columns;
an address buffer circuit for receiving an external address signal and a bias voltage, and in response, providing a buffered address signal;
an address decoding circuit, coupled to the address buffer circuit and to the plurality of memory cells, for selecting a memory cell of the plurality of memory cells in response to receiving the buffered address signal and an internal clock signal;
a clock circuit for providing the internal clock signal;
and
a power-on reset circuit, coupled to the clock circuit, to a power supply voltage terminal and to the address decoding circuit, the power-on reset circuit for receiving the power supply voltage and the bias voltage, and in response, the power-on reset circuit for setting the internal clock signal to a predetermined logic state and for decoupling the address decoding circuit from the address buffer circuit in response to a power supply voltage being below a predetermined power supply voltage level and for coupling the address decoding circuit to the address buffer circuit in response to the power supply voltage rising above the predetermined power supply voltage level and the bias voltage rising above a predetermined bias level.

3 more elements

A power-on reset circuit for an integrated circuit, the integrated circuit having first and second power supply voltage terminals for receiving a power supply voltage, and an input terminal for receiving a bias voltage, the power-on reset circuit comprising:

a model circuit, coupled between the first and second power supply voltage terminals, and having an input terminal for receiving the bias voltage, and an output terminal, the model circuit for compensating for process and temperature variations of a circuit of the integrated circuit;
a bias voltage check circuit having a first input terminal for receiving the bias voltage, a second input terminal coupled to the output terminal of the model circuit, and an output terminal, the bias voltage check circuit for determining if the bias voltage has reached a predetermined voltage during power-up of the integrated circuit;
and
a logic gate having a first input terminal coupled to the output terminal of the model circuit, a second input terminal coupled to the output terminal of the bias voltage check circuit, and an output terminal for providing a power-on reset signal in response to both the bias voltage reaching the predetermined voltage, and the power supply voltage reaching a predetermined power supply voltage level.

1 more element

A power-on reset circuit for an integrated circuit memory, comprising:

a first circuit, coupled between first and second power supply voltage terminals for receiving a power supply voltage, the first circuit having an input terminal for receiving a bias voltage, and an output terminal, the first circuit for compensating for process and temperature variations of the circuit of the integrated circuit;
a second circuit having a first input terminal coupled to the output terminal of the first circuit, a second input terminal for receiving the bias voltage, and an output terminal;
and
a logic gate having a first input terminal coupled to the output terminal of the first circuit, a second input terminal coupled to the output terminal of the second circuit, and an output terminal for providing a power-on reset signal.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 08/253,076Filed 2 Jun 1994
Granted: 19 Dec 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03K 17/223
Modifications for ensuring a predetermined initial state when the supply voltage has been applied: in field-effect transistor switches
G11C 5/143
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: detection…
G11C 8/10
Arrangements for selecting an address in a digital store: decoders
H03K 17/22
Electronic switching or gating, i.e. not by contact-making and –breaking: modifications for ensuring a predetermined initial state when the supply…