US 5,477,074 A · Semiconductor structure using local planarization with self-aligned transistors

Abstract

A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.

Claims8

Dependent claims

An integrated circuit formed on a substrate having a principal surface, comprising:

a plurality of spaced apart and insulated gate structures formed on the principal surface, an insulator being formed on the lateral and top surface of a conductive electrode of each gate structure;
a plurality of doped regions formed in the substrate, each doped region adjoining an adjacent gate structure and extending from the principal surface into the substrate;
a conductive electrical contact contacting at least one of the doped regions at the principal surface, wherein a first portion of the conductive electrical contact is formed on the insulator and overlyiny a lateral surface of the adjacent gate structure;
and
an annular structure surrounding a second portion of the conductive electrical contact and overlying the top surface of the adjacent gate structure, and being of a different material than are the conductive electrical contact and the insulator.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor structure using local planarization with self-aligned transistors

Life of this patent

Semiconductor structure using local planarization with self-aligned transistors

Life of this patent

Abstract

Claims8