Smart power integrated circuit with dynamic isolation
OwnerMario Paparo, Raffaele Zambranoinventors
Life of this patent
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Abstract
A smart power integrated circuit with dynamic isolation. A P-type isolation region surrounds the small signal devices (npn bipolar transistors and possibly other devices). This isolation region is held at ground in normal operation; but one or more pilot circuits continually monitor the collector voltages of the small-signal and power npn transistors, and instantly reconnect this isolation region, in real time, to the lowest collector voltage, whenever any of the collector voltages go below ground. Preferably a large capacitor provides a dedicated supply to the pilot circuit, so that the reconnection operation can proceed even when a power supply glitch occurs.
Claims30
An integrated circuit, comprising:
- at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors;
- at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors;
- a first switch operable to connect said p-type isolation region to ground;
- a second switch operable to connect said p-type isolation region to an n-type region of said power transistor;
- a third switch operable to connect said p-type isolation region to an n-type region of said small-signal transistor;
- a pilot circuit operatively connected to said n-type region of said small-signal transistor, to said n-type region of said power transistor, to ground, and to said first, second, and third switches;
- wherein said pilot circuit monitors the voltage of said n-type regions of said power and small-signal transistors, and accordingly operates said switches to connect said p-type isolation region to the lowest voltage of:
- ground;
- said n-type region of said power transistor;
- and said n-type region of said small-signal transistor.
An integrated circuit, comprising:
- at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors;
- at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors;
- a first switch operable to connect said p-type isolation region to ground;
- a second switch operable to connect said p-type isolation region to an n-type region of said power transistor;
- a third switch operable to connect said p-type isolation region to an n-type region of said small-signal transistor;
- a pilot circuit operatively connected to said n-type region of said small-signal transistor, to said n-type region of said power transistor, to ground, to said p-type isolation region, and to said first, second, and third switches;
- wherein said pilot circuit monitors the voltage of said p-type isolation region and said n-type regions of said power and small-signal transistors, and accordingly operates said switches to connect said p-type isolation region to the lowest voltage of:
- ground;
- said n-type region of said power transistor;
- and said n-type region of said power transistor.
An integrated circuit including a solid state two-way switch, comprising:
- first and second power transistors, each operable to connect a common substrate region, of a first conductivity type, to a respective other region of said first conductivity type;
- a first control circuit operatively connected to control said first power transistor, and a second control circuit operatively connected to control said second power transistor;
- said power transistors and control circuits all being integrated in a common body of monocrystalline semiconductor material, and said first power transistor being isolated from said first control circuit by a first isolation region, and said second power transistor being isolated from said second control circuit by a second isolation region;
- said isolation regions both having a second conductivity type;
- said first and second control circuits comprising first and second pilot circuits respectively, each connected to first and second supply voltages, and to a respective one of said isolation regions, and to said power transistor and control circuit, and to three respective switches;
- wherein each said pilot circuit operates said three respective switches to connect said respective isolation region to the most extreme voltage of:
- said first supply voltage;
- said respective other region of said power transistor;
- and said respective control circuit.
An integrated circuit, powered by negative supply voltages and a positive ground connection, comprising:
- at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors;
- at least one n-type isolation region interposed between said power transistor and at least one of said small-signal transistors;
- a first switch operable to connect said n-type isolation region to ground;
- a second switch operable to connect said n-type isolation region to a p-type region of said power transistor;
- a third switch operable to connect said n-type isolation region to a p-type region of said small-signal transistor;
- a pilot circuit connected to said p-type region of said power transistor, to ground, and to said first, second, and third switches;
- wherein said pilot circuit operates said switches to connect said n-type isolation region to the highest voltage of:
- ground;
- said p-type region of said power transistor;
- and said p-type region of said small-signal transistor.
A method for operating an integrated circuit which includes at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors, and at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors, comprising the steps of, in on-chip circuitry:
- (a.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of an N-type portion of the power transistor;
- (b.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of an N-type region of at least one of said small-signal transistors of the integrated circuit;
- (c.) operating a first N-channel switching transistor, under control of said pilot circuit, to operatively connect said p-type isolation region to said N-type portion of the power transistor, at each instant, if and only if the voltage of said N-type portion of the power transistor is below ground;
- and
- (d.) operating a second N-channel switching transistor, under control of said pilot circuit, to operatively connect the p-type isolation region to said N-type portion of at least one of said small-signal transistors, at each instant, if and only if the voltage of said N-type portion of said small-signal transistor is below ground;
- and
- (e.) operatively connecting said p-type isolation region to ground at substantially all other times.
A method for operating an integrated circuit, powered by negative supply voltages and a positive ground connection, which includes at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors, and at least one N-type isolation region interposed between said power transistor and at least one of said small-signal transistors, comprising the steps of, in on-chip circuitry:
- (a.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of a P-type portion of the power transistor;
- (b.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of a P-type region of at least one of said small-signal transistors of the integrated circuit;
- (c.) operating a first P-channel switching transistor, under control of said pilot circuit, to operatively connect the N-type isolation region to said P-type portion of the power transistor, at each instant, if and only if the voltage of said P-type portion of the power transistor is above ground;
- and
- (d.) operating a second N-channel switching transistor, under control of said pilot circuit, to operatively connect the N-type isolation region to said N-type portion of at least one of said small-signal transistors, at each instant, if and only if the voltage of said N-type portion of the small-signal transistor is below ground;
- and
- (e.) operatively connecting the N-type isolation region to ground at substantially all other times.
Dependencies are inferred from the claim text.