MIS transistor having second conductivity type source and drain regions sandwiching a channel region of a first conductivity type of a first semiconductor material formed on an insulating substrate, and a gate electrode formed on a main surface

An MIS transistor comprising a channel region of a first conductivity type semiconductor formed on an insulating substrate, source and drain regions of a second conductivity type semiconductor sandwiching said channel region therebetween, and a gate electrode formed on a main surface of said channel region with an insulating film therebetween, wherein:

• at least said source region has a heterojunction separated from a PN junction between said source and channel regions, and said source region contains a mixed crystal (Si.sub.x Ge.sub.1-x) region composed of silicon with a mixed crystal rate x and germanium, and said channel region only contains a mixed crystal (Si.sub.y Ge.sub.1-y) composed of silicon with a mixed crystal rate y and germanium, and said mixed crystal rates x and y satisfy the conditions that x<y.

An MIS transistor comprising a channel region formed on an insulating substrate and having a first conductivity type semiconductor, source and drain regions formed on said insulating substrate with said channel region therebetween and having a second conductivity type semiconductor, and a gate electrode formed on a main surface of said channel region with an insulating film therebetween, wherein:

• at least a metal electrode of said source region among the metal electrodes formed in said source and drain regions is present outside the depletion region of a PN junction between said channel and source regions and inside a diffusion length L.sub.d from a depletion edge of said depletion region, wherein L.sub.d O.

An MIS transistor comprising a first conductivity type semiconductor layer having a channel region, second conductivity type source and drain impurity regions sandwiching said channel region, and a gate electrode provided on said channel region sandwiching a gate insulating film therebetween, wherein;

• said channel region comprises a first semiconductor material of a first energy band gap, and said source region comprises only the first semiconductor material and a second semiconductor material of a second energy band gap, and a position of a heterojunction between the first and second semiconductor materials of said source region is separated from a PN junction between the first semiconductor layer of said channel region and the second conductivity type source region.