Notched insulation gate static induction transistor integrated circuit

A U-grooved insulated gate static induction transistor integrated circuit formed on a major surface of a substrate, comprising:

• an enhancement mode CMOS logic circuit including a complementary U-grooved insulated gate static induction transistor pair in which threshold voltages are determined to prevent current from flowing in a steady state;
• and
• a depletion mode CMOS logic circuit including a complementary U-grooved insulated gate static induction transistor pair in which threshold voltages are determined to cause current to slightly flow in the steady state,
• said depletion mode CMOS logic circuit being used in a circuit in which an operation frequency is higher than a maximum operation frequency of said enhancement mode CMOS logic circuit.

A U-grooved insulated gate static induction integrated circuit formed on a major surface of a substrate, comprising:

• first to fourth stages trigger flip-flop circuits having depletion mode CMOS logic circuits including complementary U-grooved insulated gate static induction transistor pairs in which threshold voltages are determined to cause current to slightly flow in a steady state,
• fifth to eighth stages trigger flip-flop circuits having enhancement mode CMOS logic circuits including complementary U-grooved insulated gate static induction transistor pairs in which threshold voltages are determined to prevent current from flowing in the steady state;
• and
• said depletion mode CMOS logic circuits being used in a circuit in which an average power dissipation in a transient state is higher than that of the steady state.