Method of dry etching InAlAs and InGaAs lattice matched to InP
AssigneeTexas Instruments Incorporated
InventorsTimothy S. Henderson, Donald L. Plumton
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AssigneeTexas Instruments Incorporated
InventorsTimothy S. Henderson, Donald L. Plumton
Estimating the term…
A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM. By this procedure, functional InAlAs/InGaAs heterojunction bipolar transistors (HBTs) and HBT circuits can be fabricated using a dry etch. Also, self-aligned small geometry structures such as, for example, emitter HBTs and ring oscillator and comparator circuits composed of HBTs and both electronic and optical devices, such as lasers, can be fabricated using the above described procedures.
A method of etching a Group III-V semiconductor structure lattice matched to InP comprising the steps of:
Dependencies are inferred from the claim text.
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Preparing bulk and homogeneous wafers: by chemical etching
Of semiconductor materials: of Group III-V materials
Generic processes or apparatus for the manufacture or treatment of devices covered
Term ended 12 Dec 2012 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates to a method of dry etching InAlAs as well as other Group III-V semiconductor compounds.
2. Brief Description of the Prior Art
An InP substrate with a 1 micrometer thick layer of InAlAs thereon was cleaned with solvents tetrachloroethylene, methanol, acetone and deionized water and a thin stripe thereon was then covered by painting a photoresist on the stripe having the rest of the wafer exposed. The wafer was then exposed to a short heating cycle to bake the photoresist for 1 minute at 100.degree. C. The wafer was then placed in a 40:1 water to ammonium hydroxide solution for 30 seconds and then rinsed in deionized water for one minute. The wafer was then placed in a standard reactive ion etching chamber and cleaned with a hydrogen plasma in standard manner under conditions of 30 SCCM hydrogen at 30 milliTorr for 2 minutes at 100 watts power. The exposed area on the substrate was then subjected to a reactive ion etch in the reactive ion etching chamber by applying a plasma composed of 30 SCCM hydrogen, 10 SCCM methane and 17 SCCM CCl.sub.2 F.sub.2 for 10 minutes at a temperature of 100.degree. C. at a power of 200 watts. The etch rate was found to be 300 Angstroms per minute with total etching being 3000 Angstroms over the 10 minute etching period.
The above noted procedure was duplicated except that an InP substrate with a 1 micrometer thick layer of InGaAs was substituted for the InAlAs layer. The etch rate was found to be 440 Angstroms per minute with a total etching of 4400 Angstroms over the 10 minute etch period.
The above noted procedure was duplicated except that a bare InP substrate was substituted for the InP substrate with the thick InAlAs layer. The etch rate was found to be 480 Angstroms over the 10 minute etch period. The substrate temperature was 30.degree. C.