A static-random-access memory array including a plurality of static-random-access memory cells, wherein each memory cell comprises:
- a semiconductor substrate;
- a first pass transistor having a first pass channel region that lies within the substrate and adjacent to a first pass field isolation section having a first pass field edge;
- a first pass channel-stop region having a first pass channel-stop doping concentration, wherein the first pass channel-stop region:
- lies within the semiconductor substrate;
- lies adjacent to the first pass field isolation section and the first pass channel region;
- and
- extends laterally beyond the first pass field edge away from the pass field isolation section by a first distance;
- a second pass transistor having a second pass channel region that lies within the substrate and adjacent to a second pass field isolation section having a second pass field edge;
- a second pass channel-stop region having a second pass channel-stop doping concentration, wherein the second pass channel-stop region:
- lies within the semiconductor substrate;
- lies adjacent to the second pass field isolation section and the second pass channel region;
- and
- extends laterally beyond the second pass field edge away from the second pass field isolation section by a second distance;
- a first latch transistor having a first latch channel region that lies within the substrate and adjacent to a first latch field isolation section having a first latch field edge;
- a first latch channel-stop region having a first latch channel-stop doping concentration, wherein the first latch channel-stop region:
- lies within the semiconductor substrate;
- lies adjacent to the first latch field isolation section and the first latch channel region;
- and
- extends laterally beyond the first latch field edge away from the first latch field isolation section by a third distance;
- a second latch transistor having a second latch channel region that lies within the substrate and adjacent to a second latch field isolation section having a second latch field edge;
- a second latch channel-stop region having a second latch channel-stop doping concentration, wherein the second latch channel-stop region:
- lies within the semiconductor substrate;
- lies adjacent to the second latch field isolation section and the second latch channel region;
- and
- extends laterally beyond the second latch field edge away from the second latch field isolation section by a fourth distance;
- and
- first and second load components selected from a group consisting of resistors, transistors, and diodes,
- wherein the memory cell has a characteristic selected from the group consisting of:
- each of the first and second pass channel-stop doping concentrations is higher than each of the first and second latch channel-stop doping concentrations;
- and
- each of the first and second distances is longer than each of the third and fourth distances.