US 5,473,183 A · Semiconductor device of a first conductivity type which has a first well of a second conductivity type formed therein and a second well of the first conductivity type formed in the first well and a pair of MOSFET formed in the first and second wells

Abstract

The present invention is directed to a CMOS inverter in which an N-FET (Qn) formed of an N-type source region (2S), a drain region (2D) and a gate electrode (2G) and a P-FET (Qp) formed of a P-type source region (3S), a drain region (3D) and a gate electrode (3G) are formed on an N-type silicon substrate (1n). A first well region (4p) is formed under the N-FET (Qn) and P-FET (Qp). Further, an N-type well region (5n) is formed on the P-FET (Qp) within the first well region (4p). Thus, an influence exerted by a back-gate effect from the substrate can be prevented completely, whereby a phase displacement relative to a pulse response to a CMOS peripheral logic circuit and a malfunction can be avoided.

Claims2

Dependent claims

A semiconductor device having a semiconductor substrate supplied with a fluctuating voltage comprising:

said semiconductor substrate of a first conductivity type;
a first well of a second conductivity type formed in said semiconductor substrate;
a second well of the first conductivity type formed in said first well;
and, wherein said first conductivity type is P-type and said second conductivity type is N-type, and wherein the device further comprising:
a pair of first MOS field effect transistors of P-type formed on the surface of said first well of N-type;
a pair of second MOS field effect transistors of N-type formed on the surface of said second well of P-type;
and
said four MOS field effect transistors being connected in a NAND circuit.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

08/301,980Filed 7 Sep 1994 · division

Priority

JP 4-03515021 Feb 1992

Granted

5 Dec 1995

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
Y10S 257/901
Active solid-state devices, e.g. transistors, solid-state diodes: mOSFET substrate bias
H10D
Inorganic electric semiconductor devices
Y10S
Technical subjects covered by former uspc cross-reference art collections [xracs] and digests

Semiconductor device of a first conductivity type which has a first well of a second conductivity type formed therein and a second well of the first conductivity type formed in the first well and a pair of MOSFET formed in the first and second wells

Life of this patent

Semiconductor device of a first conductivity type which has a first well of a second conductivity type formed therein and a second well of the first conductivity type formed in the first well and a pair of MOSFET formed in the first and second wells

Life of this patent

Abstract

Claims2