Method of making a non-volatile floating gate memory device with peripheral transistor
AssigneeSamsung Electronics Co., Ltd.
InventorsKi-Ho Gwen, Kang-Deog Suh, Jeong-Hyuk Choi
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Abstract
The present invention discloses a non-volatile memory device having a multi-level gate structure. The storage cell transistor in the cell array region and the transistor in the peripheral circuit region have the same multi-level gate structure. Also, multi-level polycrystalline silicon layers in the peripheral circuit region are connected to each other, and thus utilized as an electrically singular gate electrode. The gate structures of the two regions are formed through a single etching process, so that the decreased processing number of photolithography simplifies overall process, and reduces the damage on the field oxide layer to thereby enhance an insulating performance.
Claims7
A method for manufacturing a semiconductor transistor gate structure comprising the steps of:
- (a) forming a gate oxide layer on a substrate;
- (b) removing a portion of said gate oxide layer from a cell region to thereby expose the substrate;
- (c) forming a tunnel oxide layer on the exposed portion of the substrate;
- (d) forming a first polycrystalline silicon layer on the resultant structure after said step of forming a tunnel oxide layer;
- (e) forming an interlayer insulating film on the first polysilicon crystalline layer;
- (f) forming a second polycrystalline silicon layer on the interlayer insulating film;
- (g) partially etching the second polycrystalline silicon layer and the interlayer insulating film to form a contact hole therethrough, thereby exposing a portion of said first polycrystalline silicon layer;
- and
- (h) filling the contact hole with a third polycrystalline layer so that the first and third polycrystalline silicon layers are in electrical contact.
Dependencies are inferred from the claim text.