Loading patent…
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsIsamu Kaminaga, Shuuichi Matsue, Takahiko Arakawa, Shuuichi Katoh, Masahiro Ueda
Estimating the term…
There is disclosed a semiconductor integrated circuit device including an element-to-element line (10A) of a quadrangular (rectangular) configuration in cross section having horizontal upper and lower surfaces, with its lower surface corners on the side of a semiconductor substrate (1) chamfered on the slant. This increases the horizontal distance between adjacent lines and decreases the height of the line, permitting the adjacent line-to-line parasitic capacitance to be lower than that of the prior art line of a quadrangular configuration in cross section under the same height and line-to-line horizontal distance conditions. The line-to-substrate parasitic capacitance is also permitted to be lower for similar reasons. The semiconductor integrated circuit device is thus provided in which the parasitic capacitances generated by forming lines are minimized.
A semiconductor integrated circuit device including a plurality of semiconductor elements formed on a semiconductor substrate, said semiconductor integrated circuit device comprising:
A semiconductor integrated circuit device including a plurality of semiconductor elements formed on a semiconductor substrate, said semiconductor integrated circuit device comprising:
A semiconductor integrated circuit device including a plurality of semiconductor elements formed on a semiconductor substrate, said semiconductor integrated circuit device comprising:
Dependencies are inferred from the claim text.