Pseudo-low dielectric constant technology

Abstract

Capacitance between metal interconnects electrically contacting metal contacts in semiconductor devices comprising doped regions contacted by the metal contacts surrounded by a first interlevel dielectric layer is reduced by (a) electrically contacting a first group of the metal contacts with a first group of first metal interconnects and electrically contacting a second group of the metal contacts with a second group of first metal interconnects, the first metal interconnects formed on a first level and surrounded by a second interlevel dielectric layer; and (b) electrically contacting the second group of first metal interconnects with second metal interconnects by means of metal plugs, the metal plugs surrounded by the second interlevel dielectric layer, and the second metal interconnects surrounded by a third interlevel dielectric layer. Thus, increasing the spacing between adjacent metal interconnects, by moving alternating metal interconnects to a second level, reduces the capacitance between metal interconnects and maintains a desired RC delay. In its simplest form, the number of contacts/vias masking layers as well as metal conductor masking layers is doubled compared to prior art processes. However, employing improved design and layout methodologies, three new metal layers will be used to do the job of two old metal layers. The cost of manufacturing is increased, but the speed is improved by up to 50% without relying on any new, untried material systems.

Dependencies are inferred from the claim text.