Semiconductor device having piezo resistance
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakashi Ipposhi, Tadashi Nishimura
Life of this patent
Estimating the term…
Abstract
Disclosed herein a semiconductor pressure sensor, which is capable of carrying out temperature compensation in high accuracy, having a piezo resistance layer consisting of a single crystal layer formed by lateral seeding. In this semiconductor pressure sensor, a piezo resistance is so formed as to contain no crystal sub-grain boundary. Thus prevented is inconvenience of reduction in resistance temperature coefficient, which is caused when the piezo resistance contains the crystal sub-grain boundary. Thus, the piezo resistance can be set at a high resistance temperature coefficient, whereby a semiconductor pressure sensor capable of carrying out temperature compensation in high accuracy is obtained.
Claims11
A semiconductor device comprising:
- a single crystal semiconductor substrate having a seed crystal region;
- an insulating layer being formed on said single crystal semiconductor substrate;
- and
- a piezo resistance layer, having piezo characteristics, consisting of a single crystal layer being formed by laterally growing single crystals from said seed crystal region on said insulating layer,
- said piezo resistance layer being so formed as to have one or more crystal sub-grain boundaries therein, and contacts which define a current path therebetween, said contacts being selectively positioned so that any portion of the current path is not traversed by any crystal sub-grain boundary in said piezo resistance layer.
A semiconductor device comprising:
- a single crystal semiconductor substrate having a seed crystal region;
- an insulating layer being formed on said single crystal semiconductor region;
- and
- a piezo resistance layer, having piezo characteristics, consisting of a single crystal layer being formed by laterally growing single crystals from said seed crystal region on said insulating layer,
- said piezo resistance layer being so formed as to have one or more crystal sub-grain boundaries therein directed in the same direction as the current flow path in the piezo resistance layer.
A semiconductor device comprising:
- a single crystal semiconductor substrate having a seed region;
- an insulating layer being formed on said single crystal semiconductor substrate;
- and
- a piezo resistance layer, having piezo characteristics, including a pair of contact regions positioned at ends thereof, respectively, and consisting of a single crystal layer having subgrain boundaries only at the ends of the current path between said pair of contact regions.
Dependencies are inferred from the claim text.