Semiconductor memory device and manufacturing method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYutaka Ikeda
Life of this patent
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Abstract
Disclosed is a semiconductor memory device having such a structure that a voltage variation on a bit line does not affect a voltage on another bit line. A gate electrode portion branches and extends laterally from a word line and extends almost in parallel with the bit line. First and second impurity regions of a field effect transistor are formed in regions between adjacent word lines, with the gate electrode portion therebetween. A capacitor electrically connected to the second impurity region is formed to cover the bit lines. Since the capacitor is between adjacent bit lines, no voltage variation on one bit line affects a voltage on the other bit lines.
Claims14
A semiconductor memory device comprising:
- a semiconductor substrate having a main surface;
- a word line formed on said main surface;
- a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface and spaced apart from said first impurity region to define a channel region therebetween, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region, the entire side surface of said gate electrode portion being defined by a straight line perpendicular to said word line;
- a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate;
- and
- a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,
- at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface.
A semiconductor memory device comprising:
- a semiconductor substrate having a main surface;
- a word line formed on said main surface;
- a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface and spaced apart from said first impurity region to define a channel region therebetween, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region, a material of said word line having a lower resistance value than a material of said gate electrode portion;
- a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate, and
- a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween.
A semiconductor memory device, comprising:
- a semiconductor substrate having a main surface;
- a word line formed on said main surface;
- a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, said first and second impurity regions and said channel region defining an active area, and a gate electrode portion, said electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region;
- a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate;
- and
- a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,
- at least one of said first and second electrode layers being formed at a level equal to or higher than the level of said bit line formed on said substrate,
- wherein said word line extends parallel to said active area.
Dependencies are inferred from the claim text.