Dual-channel emitter switched thyristor with trench gate

A semiconductor switching device comprising:

• a semiconductor substrate having first and second opposing faces;
• a trench in said substrate at said second face;
• an anode contact on said first face;
• a cathode contact on said second face;
• a thyristor between a bottom of said trench and said first face, said thyristor having a floating emitter region of first conductivity type at the trench bottom;
• and
• a dual inversion-layer channel insulated-gate field effect transistor having a gate electrode in said trench, a gate electrode insulating layer extending adjacent a sidewall of said trench, a first active region of first conductivity type in said substrate, opposite said gate electrode insulating layer, and second and third active regions of second conductivity type in said substrate, opposite said gate electrode insulating layer, wherein said first active region extends between said second and third active regions and forms P-N junctions therewith, wherein the application of a turn-on bias signal to said gate electrode electrically connects said floating emitter region to said cathode contact by a first conductivity type inversion-layer channel in said second active region and a first conductivity type inversion-layer channel in said third active region and wherein the application of a turn-off bias signal to said gate electrode electrically connects said third active region to said second active region by a second conductivity type inversion-layer channel in said first active region.

A semiconductor switching device comprising:

• a semiconductor substrate having first and second opposing faces;
• an anode region in said substrate adjacent said first face;
• a first base region of first conductivity type in said substrate, on said anode region;
• a trench in said substrate at said second face, said trench having a trench bottom and first and second trench sidewalls;
• a floating emitter region of first conductivity type and a second base region of second conductivity type at said trench bottom, said second base region extending between said first base region and said floating emitter region and forming P-N junctions therewith;
• and
• a dual inversion-layer channel field effect transistor in said trench, said transistor having first and second conductivity type active regions in said substrate, adjacent the first and second sidewalls of the trench, respectively, wherein said first base region comprises said first conductivity type active region, wherein said second base region comprises said second conductivity type active region, wherein the application of a turn-on gate bias signal to said transistor causes the formation of a first conductivity type inversion-layer channel in said second base region, adjacent the second sidewall, and wherein the application of a turn-off gate bias signal to said transistor causes the formation of a second conductivity type inversion-layer channel in said first base region, adjacent the first sidewall.

A semiconductor switching device comprising:

• a semiconductor substrate having first and second opposing faces;
• an anode region in said substrate adjacent said first face;
• first and second adjacent trenches in said substrate at said second face, and wherein each of said trenches has trench bottoms and first and second trench sidewalls;
• a first base region of first conductivity type in said substrate, said first base region extending between said anode region and the first sidewall of said first trench and between said anode region and the first sidewall of said second trench;
• first and second overlapping floating emitter regions of first conductivity type at the bottoms of said first and second trenches, respectively;
• overlapping second base regions of second conductivity type at the bottoms of said first and second trenches, said overlapping second base regions extending between said first base region and said overlapping floating emitter regions;
• a cathode region of first conductivity type on said overlapping second base regions and extending to said second face, said cathode region extending adjacent the second sidewalls of said first and second trenches;
• first and second diverter regions of second conductivity type in said substrate which extend adjacent the first sidewalls of said first and second trenches, respectively, and form P-N junctions with said first base region;
• and
• first and second dual inversion-layer channel field effect transistors in said first trench and in said second trench, respectively,
• wherein the application of a turn-on gate bias signal to said first and second dual-channel field effect transistors causes the formation of first conductivity type inversion-layer channels adjacent the second sidewalls;
• and
• wherein the application of a turn-off gate bias signal to said first and second dual-channel field effect transistors causes the formation of second conductivity type inversion-layer channels in said first base region and wherein one of said second conductivity type inversion-layer channels extends between said overlapping second base regions and said first diverter region and the other of said second conductivity type inversion-layer channels extends between said overlapping second base regions and said second diverter region.

A semiconductor switching device comprising:

• a semiconductor substrate having first and second opposing faces;
• an anode region in said substrate adjacent said first face;
• a first base region of first conductivity type in said substrate, on said anode region;
• first and second adjacent trenches in said substrate at said second face, and wherein each of said trenches has trench bottoms and first and second opposing trench sidewalls;
• a common floating emitter of first conductivity type at the bottoms of said first and second trenches;
• a common second base of second conductivity type surrounding said common floating emitter and forming a P-N junction therewith;
• a cathode region of first conductivity type in said substrate, between the second sidewalls of said first and second trenches;
• first and second diverter regions of second conductivity type in said substrate, said diverter regions forming P-N junctions with said first base region of first conductivity type and extending adjacent the first sidewalls of said first and second adjacent trenches but not extending adjacent the second sidewalls of said first and second adjacent trenches;
• and
• first and second dual-channel field effect transistors having insulated gate electrodes, in said first trench and in said second trench, respectively, so that the first sidewalls of said first and second trenches define an interface between said insulated gate electrodes and said first base region.

An emitter switched thyristor, comprising:

• a semiconductor substrate having first and second opposing faces;
• anode and cathode contacts on said first and second faces, respectively;
• anode and cathode regions of opposite conductivity type in said substrate, adjacent said first and second faces, respectively;
• a plurality of adjacent trenches in said substrate, at said second face;
• a plurality of electrically insulated gate electrodes in respective ones of said plurality of trenches;
• a first base region of same conductivity type as said cathode region in said substrate, said first base region forming a P-N junction with said anode region and extending between adjacent ones of said trenches so that sidewalls of said trenches define a plurality of interfaces between said first base region and said plurality of electrically insulated gate electrodes;
• a plurality of floating emitter regions of same conductivity type as said cathode region in said substrate, each of said floating emitter regions extending adjacent a bottom of said plurality of trenches;
• a plurality of second base regions of same conductivity type as said anode region in said substrate, each of said second base regions surrounding a respective floating emitter region at a bottom of said plurality of trenches and forming a P-N junction therewith;
• a plurality of third base regions of same conductivity type as said anode region in said substrate, each of said third base regions extending between the sidewalls of adjacent ones of said plurality of trenches, forming respective P-N junctions with said first base region and forming respective ohmic contacts with said cathode contact at the second face;
• wherein the application of a turn-on bias signal to said plurality of insulated gate electrodes causes the formation of a plurality of first conductivity type inversion-layer channels in said third base regions which electrically connect said first base region to said cathode contact;
• and
• wherein the application of a turn-off bias signal to said plurality of insulated gate electrodes causes the formation of a plurality of second conductivity type inversion-layer channels in said first base region which electrically connect said plurality of second base regions to said plurality of third base regions.