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US 5,470,793 AGranted
Method of via formation for the multilevel interconnect integrated circuits
AssigneeSGS-Thomson Microelectronics S.A.
InventorAlexander Kalnitsky
Life of this patent
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Abstract
A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.
Claims4
A method for forming an integrated circuit contact structure, comprising the steps of:
- forming a metal conductive element over a lower insulating layer;
- forming a conformal oxide layer over said metal conductive element and said lower insulating layer;
- forming a layer of spin on glass over said conformal oxide layer;
- forming a barrier layer over said conformal oxide layer;
- forming an insulating layer over said barrier layer, wherein the barrier layer is made of a material that is not etched by a wet etch that etches said insulating layer;
- depositing and patterning a photoresist layer over said insulating layer;
- performing a wet etch part way through the insulating layer in a region defined by the patterned photoresist layer, leaving a remainder of the insulating layer which is not etched through;
- and
- performing an anisotropic etch through the remainder of the insulating layer, the barrier layer, and the conformal oxide layer in the region defined by the patterned photoresist layer to expose a portion of the metal conductive element;
- wherein the insulating layer has a crack in the region defined by the patterned photoresist layer, wherein the crack extends through the insulating layer to the barrier layer, and wherein, during the step of performing a wet etch, the barrier layer acts as an etch stop for etchant which moves through the crack.
7 more elements
Dependencies are inferred from the claim text.