Method of manufacturing a semiconductor device

A method of forming a memory cell within a semiconductor layer which includes a top surface, said method comprising the steps of:

• forming a first depression in said semiconductor layer such that said first depression is disposed within said semiconductor layer below said top surface;
• forming a second depression continuous to said first depression within said semiconductor layer, said second depression formed deeper than said first depression;
• forming a first doped region in said semiconductor layer adjacent said second depression;
• forming an insulating layer within said first and second depressions;
• forming a conductor adjacent said insulating layer within said first and second depressions;
• forming an insulating film on top of said conductor at an interface wherein said interface is formed inside said first depression below said top surface;
• forming a second doped region in said semiconductor layer and spaced from said first doped region by a channel region;
• and
• forming a gate over said channel region.

A method of forming a semiconductor device within a semiconductor layer which includes a top surface, said method comprising the steps of:

• forming a first depression in said semiconductor layer and extending below said top surface;
• forming a second depression in said semiconductor layer and linked to said first depression, said second depression formed deeper than said first depression;
• forming a first conductor within said second depression thereby creating a third depression within said second depression;
• forming a second conductor within said first and third depressions, said second conductor insulated from said first conductor;
• and
• forming an insulating film on top of said second conductor at an interface wherein the interface between the insulating film and the second conductor is formed inside the first depression.

A method of forming a memory cell within a semiconductor layer which includes an uppermost surface, said method comprising the steps of:

• forming a shallow depression within said semiconductor layer, said shallow depression having a sidewall;
• etching a portion of said semiconductor layer adjacent said shallow depression sidewall thereby forming a deep trench which overlaps said shallow depression, said deep trench extending further within said semiconductor layer than said shallow depression;
• forming a first conductive layer along a sidewall within said deep trench;
• forming a dielectric layer over said first conductive layer within said deep trench;
• forming a second conductive layer within said shallow depression and said deep trench, said second conductive layer having an uppermost surface disposed below said uppermost surface of said semiconductor layer;
• forming an insulating layer over said second conductive layer;
• forming a gate overlying a channel region within said semiconductor layer and spaced from said deep trench;
• and
• forming a first and second doped regions within said semiconductor layer adjacent said gate, said first doped region formed adjacent said deep trench and said second doped region spaced from said doped region by said channel region.

A method of making a semiconductor storage device comprising the steps of:

• forming a first groove in a semiconductor substrate of one conductive type;
• forming a second groove deeper than the first groove, said second groove being stacked within said first groove;
• forming an insulating film within said second groove, said insulating film provided so as to expose a portion of said substrate;
• forming an accumulating electrode along the walls of said second groove wherein said accumulating electrode is brought into contact with the substrate at said portion which was exposed;
• adding impurities of the conductive type opposite that of the substrate to the substrate in said exposed section;
• burying an electrode in said first and second grooves wherein said electrode and said accumulating electrode are separated by a capacitor insulating film;
• and
• providing a MOS transistor within said substrate wherein, said MOS transistor includes first and second source/drain regions of said opposite conductive type, wherein said first source/drain region contacts said accumulating electrode.