US 5,470,774 AGranted

Fabrication method of a read-only semiconductor memory device

AssigneeNEC Corporation

InventorMasao Kunitou

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Abstract

A fabrication method of a semiconductor memory device in which the punch-through phenomenon is difficult to occur in uncoded or unwritten memory cells. First impurity-doped regions for coding are formed in channel areas of selected ones of first MOS transistors in the memory cell area, using a patterned photoresist film as a mask, respectively. Second impurity-doped regions for threshold adjustment are formed in channel areas of unselected ones of the first transistors and second transistors in the peripheral circuit area, using a patterned photoresist film as a mask, respectively. During the process of forming the second impurity-doped regions, the dopant doped for threshold adjustment through the selected ones of the first transistors into the substrate forms third impurity-doped regions apart from the channel areas of the selected ones of the first transistors, respectively. The third impurity-doped regions serve to restrain the first dopant doped into the selected ones of the first transistors from laterally diffusing in the substrate, preventing the punch-through phenomenon.

Claims16

Dependent claims

A fabrication method of a semiconductor memory device, said method comprising the steps of:

(a) preparing memory cells formed of first MOS transistors and peripheral circuits formed of second MOS transistors on a semiconductor substrate of a first conductivity type, said memory cells being formed in a memory cell area of said substrate, said peripheral circuits being formed in a peripheral circuit area of said substrate;
(b) forming a photoresist film on said substrate to cover said memory cell area and said peripheral circuit area;
(c) patterning said photoresist film to have windows so that selected ones of said first transistors to be coded are exposed from said photoresist film through said windows, respectively;
(d) selectively doping a first dopant of a second conductivity type for coding into said selected ones of said first transistors using said patterned photoresist film as a mask, so that first impurity-doped regions of said second conductivity type being formed in channel areas of said selected ones of said first transistors, respectively, said second conductivity type being opposite in polarity to said first conductivity type;
and
(e) doping a second dopant of said first conductivity type for threshold adjustment into said first transistors and said second transistors through said patterned photoresist film, so that second impurity-doped regions of said first conductivity type being formed in channel areas of unselected ones of said first transistors and said second transistors, respectively;
wherein
during said step of (e), said second dopant doped through said selected ones of said first transistors forms third impurity-doped regions of said first conductivity type apart from said channel areas of said selected ones of said first transistors in said substrate, respectively;
and wherein
said third impurity-doped regions serve to restrain said first dopant doped into said selected ones of said first transistors in said step of (d) from laterally diffusing in said substrate.

7 more elements

A fabrication method of a semiconductor memory device, said method comprising the steps of:

(a) preparing memory cells formed of first MOS transistors and peripheral circuits formed of second MOS transistors on a semiconductor substrate of a first conductivity type, said memory cells being formed in a memory cell area of said substrate, said peripheral circuits being formed in a peripheral circuit area of said substrate;
(b) forming an interlayer insulator film on said substrate to cover said memory cell area and said peripheral circuit area;
(c) heating said interlayer insulator film for reflowing said interlayer insulator film;
(d) forming a photoresist film on said interlayer insulator film thus reflown to cover said memory cell area and said peripheral circuit area;
(e) patterning said photoresist film to have windows so that said windows are placed over selected ones of said first transistors to be coded, respectively;
(f) selectively doping a first dopant of a second conductivity type for coding into said selected ones of said first transistors through said interlayer insulator film using said patterned photoresist film as a mask, so that first impurity-doped regions of said second conductivity type being formed in channel areas of said selected ones of said first transistors, respectively, said second conductivity type being opposite in polarity to said first conductivity type;
and
(g) doping a second dopant of said first conductivity type for threshold adjustment into said first transistors and said second transistors through said patterned photoresist film and said interlayer insulator film, so that second impurity-doped regions of said first conductivity type being formed in channel areas of unselected ones of said first transistors and said second transistors, respectively;
wherein
during said step of (g), said second dopant doped through said selected ones of said first transistors forms third impurity-doped regions of said first conductivity type apart from said channel areas of said selected ones of said first transistors in said substrate, respectively;
and wherein
said third impurity-doped regions serve to restrain said first dopant doped into said selected ones of said first transistors in said step of (f) from laterally diffusing in said substrate.

9 more elements

Dependencies are inferred from the claim text.