Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch
AssigneeAdvanced Micro Devices, Inc.
InventorsDavid K. Y. Liu, Yu Sun, Chi Chang
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Abstract
A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
Claims8
A method for protecting a stacked gate edge to minimize damage to a tunnel oxide and to maintain source junction uniformity of a semiconductor device comprising the sequential steps of:
- (a) providing the stacked gate edge on the semiconductor device;
- (b) performing a source implant on the semiconductor device;
- (c) providing a spacer on the stacked gate edge;
- and
- (d) providing a self aligned source (SAS) etch on the semiconductor device.
Dependencies are inferred from the claim text.