Deflection apparatus for raster scanned CRT displays

Deflection apparatus for a raster scanned cathode ray tube display, the apparatus comprising:

• a ramp generator having a flyback circuit (T2, Lc, Cf;
• T2, Ly, Cf) including a first inductor (Lc;
• Ly) connected in series with a first transistor switch (T2), the first transistor switch (T2) being responsive to a line drive signal (LINE) to alternately open and close a current path through the first inductor (Lc;
• Ly) between a first voltage level (B+) and a second voltage level (0 V) lower than the first voltage level (B+) to generate a raster scan current signal in a deflection coil (Ly) of the display, the amplitude of the raster scan current signal being determined as a function of the first voltage level (B+) and the frequency of the line drive switching signal (LINE), and a boost circuit (T3, L, D1, C1;
• T3, L, D1, Cs) connected to the flyback circuit (T2, Lc, Cf;
• T2, Ly, Cf), the boost circuit (T3, L, D1, C1;
• T3, L, D1, Cs) comprising a second inductor (L) connected in series with a second transistor switch (T3), the second transistor switch (T3) being responsive to a pulse signal (PWM) synchronized to the line drive signal (LINE) to alternately open and close a current path through the second inductor (L) between the second voltage level (0 V) and a third voltage level higher than the second voltage level (Vin) to generate the first voltage level (B+), the first voltage level (B+) being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM);
• and
• a regulator connected (230) to the flyback circuit (T2, Lc, Cf;
• T2, Ly, Cf) and the boost circuit (T3, L, C1;
• T3, L, Cs) for varying the width of the pulses of the pulse signal (PWM) as a function of the amplitude of the line scan signal to maintain a constant raster line width as the frequency of the line drive signal is varied;
• wherein the regulator comprises:
• a feedback circuit connected to the flyback circuit for generating a feedback signal as a function of the amplitude of the voltage impulse signal;
• an error amplifier connected to the feedback circuit for generating an error signal as a function of the difference between the feedback signal and a reference level, and a pulse width modulator connected to the error amplifier and the boost circuit for modulating the width of the pulse signal as a function of the error signal;
• wherein the pulse width modulator (R1, 610, 620) comprises:
• a current sensor (R1) connected to the boost circuit (T3, L, D1, C1) for generating a ramp signal as a function of current flowing in the second current path;
• a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal;
• and a latch (620) connected to the boost circuit (T3, L, D1, C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).

Apparatus for generating an anode voltage for a CRT display, the generator comprising:

• a flyback circuit (T2', Tr1) including a transformer (Tr1) having a primary winding connected in series with a first transistor switch (T2'), the first transistor switch (T2') being responsive to a line drive switching signal (LINE) to alternately open and close a current path through the primary winding between a first voltage level (B+') and a second voltage level (0 V) lower than the first voltage level (B+') to generate a voltage impulse signal across the primary winding, the amplitude of the voltage impulse signal being determined as a function of the first voltage level (B+') and the frequency of the line drive switching signal (LINE), and
• a boost circuit (L', T1', D1', C') connected to the flyback circuit (T2', Tr1), the boost circuit (L', T1', D1', C') comprising an inductor (L') connected in series with a second transistor switch (T1'), the second transistor switch (T1') being responsive to a pulse signal (PWM') synchronised to the line drive signal (LINE) to alternately open and close a current path through the inductor (L') between the second voltage level (0 V) and a third voltage level (Vin) higher than the second voltage level (0 V) to generate the first voltage level (B+'), the first voltage level (B+') being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM');
• and
• a regulator (700, 710, 720) connected to the flyback circuit (T2', Tr1) and the boost circuit (L', T1', D1', C') for varying the width of the pulses of the pulse signal (PWM') as a function of the amplitude of the voltage impulse signal to maintain a constant anode voltage as the frequency of the line drive signal is varied;
• wherein the regulator comprises:
• a feedback circuit connected to the flyback circuit for generating a feedback signal as a function of the amplitude of the voltage impulse signal;
• an error amplifier connected to the feedback circuit for generating an error signal as a function of the difference between the feedback signal and a reference level, and a pulse width modulator connected to the error amplifier and the boost circuit for modulating the width of the pulse signal as a function of the error signal;
• wherein the pulse width modulator (R1, 610, 620) comprises:
• a current sensor (R1) connected to the boost circuit (T3, L, D1, C1) for generating a ramp signal as a function of current flowing in the second current path;
• a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal;
• and a latch (620) connected to the boost circuit (T3, L, D1, C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).