Integrated circuit with layered superlattice material and method of fabricating same

A method of fabricating an integrated circuit, said method comprising the steps of:

• providing a substrate;
• forming a capacitor on said substrate, said capacitor including an intermediate layer comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials;
• spin coating a layer of insulator over said capacitor;
• treating said insulator in three or more heating steps to form a solid insulating layer over said capacitor, the temperature of each heating step being at a higher temperature than the previous heating step.

A method of fabricating an integrated circuit, said method comprising the steps of:

• providing a substrate;
• forming a transistor on said substrate, said transistor including an active area;
• forming a first insulating layer overlying said transistor;
• forming a capacitor on said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said capacitor including a first electrode, an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials, and a second electrode overlying said intermediate layer;
• forming a second insulating layer overlying said capacitor;
• thereafter
• performing a first etch through a first mask pattern to form a contact hole to at least one of said first electrode and said second electrode;
• performing a second etch through a second etch pattern to form a contact hole to said active area;
• and
• forming a wiring layer contacting said active area and one of either said first electrode or said second electrode.

A method of fabricating an integrated circuit, said method comprising the steps of:

• providing a substrate comprising silicon;
• forming a transistor on said substrate, said transistor including an active area;
• forming a first insulating layer overlying said transistor;
• forming a capacitor on said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said capacitor including a first electrode, an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials, and a second electrode overlying said intermediate layer;
• thereafter
• forming a second insulating layer overlying said capacitor;
• forming contact holes to said active area and to at least one of said first electrode and said second electrode;
• forming a wiring layer contacting said active area and one of either said first electrode or said second electrode;
• and
• said method further including an anneal step between said step of forming a second insulating layer and said step of forming a wiring layer.

A method of fabricating an integrated circuit, said method comprising the steps of:

• providing a silicon substrate;
• forming a transistor on said substrate, said transistor including a first active area;
• forming a first insulating layer overlying said transistor, said first insulating layer comprising a material from the group comprising BPSG and SOG;
• forming a first electrode overlying said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said first electrode consisting essentially of platinum;
• forming an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials;
• forming a second electrode overlying said intermediate layer;
• forming a second insulating layer overlying said capacitor, said second insulating layer comprising SOG;
• forming a wiring layer making electrical contact with said active area and one of either said first electrode and second electrode, said wiring layer comprising platinum.

A method of fabricating an integrated circuit comprising:

• providing a substrate comprising silicon;
• forming a MOS device on said substrate;
• forming a first insulating layer over said MOS device;
• forming a second device over said first insulating layer without first providing a contact hole through said first insulating layer to said MOS device, said second device comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials;
• forming a second insulating layer overlying said MOS device and said second device;
• forming a first wiring layer contact hole through said first and second insulating layers to said MOS device and a second wiring layer contact hole through said second insulating layer to said second device;
• forming a first wiring metal layer in at least one of said contact holes;
• annealing said integrated circuit to improve the electrical characteristics of said MOS device;
• forming a second wiring metal layer in one or more of said contact holes to connect said MOS device to said second device;
• and
• completing said integrated circuit.