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US 5,465,189 AGranted
Low voltage triggering semiconductor controlled rectifiers
AssigneeTexas Instruments Incorporated
InventorsThomas L. Polgreen, Amitava Chatterjee, Ping Yang
Life of this patent
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Abstract
A new semiconductor controlled rectifier which may be used to provide on-chip protection against ESD stress applied at the input, output, power supply pins or between any arbitrary pair of pins of an integrated circuit is disclosed. The structure which has the lowest breakdown voltage for a given technology is incorporated into the SCR enabling a SCR trigger voltage determined by the lowest breakdown-structure.
Claims37
An integrated circuit comprising:
- a device for which ESD protection is desired, said device including at least one MOS transistor;
- a lateral semiconductor controlled rectifier coupled to said device, said semiconductor controlled rectifier including a common region;
- a MOS-like structure integral with said semiconductor controlled rectifier, said MOS-like structure also including said common region, said semiconductor controlled rectifier being operable to be triggered by a current generated when said MOS-like structure is in avalanche breakdown.
A silicon controlled rectifier comprising:
- a semiconductor layer, said semiconductor layer comprising silicon of a first conductivity type;
- at least two semiconductor regions in spaced apart relation formed in said semiconductor layer, said at least two semiconductor regions comprising silicon of a second conductivity type, said second conductivity type different than said first conductivity type;
- a gate formed over a region of said semiconductor layer between said semiconductor regions;
- a gate insulator interposed between said gate and said semiconductor layer;
- a well region of said second conductivity type formed in said semiconductor layer and at least partially overlapping a first of said at least two semiconductor regions;
- and
- third and fourth semiconductor regions formed in said well region, said third semiconductor region having said first conductivity type and said fourth semiconductor region having said second conductivity type.
4 more elements
A semiconductor controlled rectifier comprising:
- a semiconductor layer of a first conductivity type;
- a first doped region of a second conductivity type formed in said semiconductor layer, said first conductivity type different than said second conductivity type;
- a second doped region of said second conductivity type formed in said semiconductor layer and spaced from said first doped region;
- a gate region formed overlying said semiconductor layer between said first and second doped regions;
- an insulating region formed between said gate and said semiconductor layer;
- a well region of said second conductivity type formed in said semiconductor layer and partially overlapping said second doped region;
- and
- a third doped region of said first conductivity type formed in said well region.
5 more elements
A silicon controlled rectifier comprising:
- a first n-type silicon region;
- a first p-type silicon region adjacent said first n-type region;
- an insulating layer formed over said first p-type region;
- a gate formed over said insulating layer;
- a second n-type silicon region adjacent said first p-type region such that said first n-type region is spaced from said second n-type region by said first p-type region, said second n-type region comprising an n-doped region and an n-well region, said n-doped overlapping said n-well region;
- and
- a second p-type silicon region adjacent said second n-type region such that said first p-type region is spaced from said second p-type region by said second n-type region, said second p-type region formed within said n-well region.
4 more elements
Dependencies are inferred from the claim text.