Low-power inverter for crystal oscillator buffer or the like

A low-power inverter for a circuit such as a crystal oscillator buffer, comprising:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate, and a drain coupled to said output node for providing said output signal;
• a first N-channel transistor having a drain coupled to said output node, a gate coupled to said input node, and a source coupled to a second power supply voltage terminal;
• a source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first P-channel transistor, said source follower stage comprising:
• a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a first predetermined current;
• a second P-channel transistor having a source coupled to said second terminal of said first current source and to said gate of said first P-channel transistor, a gate coupled to said input node for receiving said input signal, and a drain;
• and
• a second current source having a first terminal coupled to said drain of said second P-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current, and
• clamp means coupled to said first power supply voltage terminal and to said gate of said first P-channel transistor, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.

A low-power inverter for a circuit such as a crystal oscillator buffer, comprising:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate, and a drain coupled to said output node for providing said output signal;
• a first N-channel transistor having a drain coupled to said output node, a gate, and a source coupled to a second power supply voltage terminal;
• a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current;
• a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said input node, and a source coupled to said gate of said first N-channel transistor;
• a second current source having a first terminal coupled to said gate of said first N-channel transistor and to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current;
• a third N-channel transistor having a drain coupled to said gate of said first N-channel transistor, a gate coupled to said gate of said first N-channel transistor, and a source coupled to said second power supply voltage terminal;
• a third current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a third predetermined current;
• a second P-channel transistor having a source coupled to said second terminal of said second current source and to said gate of said first P-channel transistor, a gate coupled to said input node, and a drain coupled to said second power supply voltage terminal;
• and
• a third P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain coupled to said gate of said first P-channel transistor.

An oscillator comprising:

• a first node for being coupled to a first terminal of a crystal;
• a second node for being coupled to a second terminal of a crystal;
• first and second power supply voltage terminals;
• a first P-channel transistor having a source coupled to said first power supply voltage terminal, a gate, and a drain coupled to said second node;
• a first N-channel transistor having a drain coupled to said second node, a gate, and a source coupled to said second power supply voltage terminal;
• a first source follower stage having an input terminal coupled to said first node, and an output terminal coupled to said gate of said first N-channel transistor, said first source follower stage comprising;
• a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current;
• a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said first node, and a source coupled to said gate of said first N-channel transistor;
• and
• a second current source having a first terminal coupled to said gate of said first N-channel transistor and to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current;
• first clamp means coupled to said gate of said first N-channel transistor and to said second power supply voltage terminal, for clamping a voltage at said gate of said first N-channel transistor to be less than, a first predetermined voltage greater than a voltage of said second power supply voltage terminal, thereby limiting a drain-to-source current of said first N-channel transistor;
• a second source follower stage having an input terminal coupled to said first node, and an output terminal coupled to said gate of said first P-channel transistor;
• and
• second clamp means coupled to said gate of said first P-channel transistor and to said first power supply voltage terminal, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a second predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.

A low-power inverter for a circuit such as a crystal oscillator buffer, comprising:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a first MOS transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a gate coupled to said input node, and a second current electrode coupled to said output node for providing said output signal;
• a second MOS transistor of a second conductivity type having a first current electrode coupled to said output node, a gate, and a second current electrode coupled to a second power supply voltage terminal;
• a first source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said second MOS transistor, comprising:
• a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current;
• and
• a third MOS transistor of said second conductivity type having a first current electrode coupled to said second terminal of said first current source, a gate coupled to said input node, and a second current electrode coupled to said gate of said second MOS transistor;
• and
• a fourth MOS transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third MOS transistor, a gate coupled to said second current electrode of said third MOS transistor, and a second current electrode coupled to said second power supply voltage terminal.