Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal

A dynamic random access memory device having a plurality of memory storage cells for storing electronic data, the dynamic random access memory device performing a refresh in order to refresh the data, said dynamic random access memory device having an oscillator circuit for generating an internal clock signal for controlling a timing of the refresh, the oscillator circuit comprising:

• a) a self-refresh memory array having control memory cells capable of charge and discharge;
• b) a current source for charging each of the control memory cells to a potential;
• c) a switching device interposed between said self-refresh memory array and said current source, said switching device, when actuated, allowing current to pass between said current source and said self-refresh memory array to perform the charging of each of said control memory cells, and said switching device electrically isolating said current source from said self-refresh memory array when deactuated;
• and
• d) a monitor circuit for monitoring the potential on the control memory cells and for generating a first signal in response to the potential on the control memory cells reaching a first trip point during the charging of each of said control memory cells and for generating a second signal in response to the potential on the control memory cells reaching a second trip point during the isolating of said current source from said self-refresh memory array, said internal clock signal comprising said first signal and said second signal.

A dynamic random access memory device having a plurality of memory storage cells for storing electronic data, the dynamic random access memory device performing a refresh in order to refresh the data, said dynamic random access memory device having an oscillator circuit for generating an internal clock signal for controlling a timing of the refresh, the oscillator circuit comprising:

• a) a control memory cell capable of charge and discharge;
• b) a current source for charging said control memory cell to a potential;
• c) a monitor circuit for monitoring the potential on said control memory cell to determine when the potential of said control memory cell reaches a trip point;
• and
• d) a discharge circuit for discharging said control memory cell in response to the potential on said control memory cell reaching the trip point, a rate of the charge and the discharge of said control memory cell determining a frequency of the internal clock signal.

A method for generating a self-refresh timing signal in a dynamic random access memory device comprising the following steps:

• a) charging a control memory cell to a potential;
• b) monitoring the potential of the control memory cell;
• c) discharging the potential of the control memory cell when the potential of the control memory cell reaches a trip point said charging and discharging creating a charge-discharge cycle having a period;
• d) counting the cycles of said charge-discharge cycle to generate the self-refresh timing signal after a desired number of the cycles have been counted;
• and
• e) refreshing memory storage cells of said dynamic random access memory in response to said self-refresh timing signal.

A method for generating a self-refresh timing signal in a dynamic random access memory comprising the following steps:

• a) sourcing current between a control memory cell and a current source;
• b) charging the control memory cell to a potential with said current;
• c) monitoring the potential of the control memory cell;
• d) terminating said step of sourcing in response to the potential of the control memory cell reaching a first trip point;
• e) discharging the potential of the control memory cell in response to the potential of the control memory cell reaching the first trip point;
• f) terminating said step of discharging in response to the potential of the control memory cell reaching a second trip point;
• g) recharging the control memory cell in response to the potential of the control memory cell reaching the second trip point;
• h) counting a number of periods of said charging and said discharging;
• i) issuing a self-refresh timing signal in response to a desired number of said periods counted;
• and
• j) refreshing memory storage cells of said dynamic random access memory in response to said self-refresh timing signal.

A method for refreshing a dynamic random access memory device having memory storage cells for storing data, the method comprising the following steps:

• a) fabricating a control memory array to have a reaction to voltage and temperature changes representative of a reaction of the memory storage cells to said voltage and said temperature changes;
• b) charging said control memory array;
• c) discharging said control memory array;
• d) generating a self-refresh cycle signal in response to said steps of charging and discharging;
• e) generating a self-refresh mode signal in response to said steps of charging and discharging;
• f) enabling the self-refresh cycle signal with said self-refresh mode signal when an externally generated row address strobe signal is active;
• and
• g) refreshing the dynamic random access memory device in response to the self-refresh cycle signal.

A method for refreshing a dynamic random access memory device having memory storage cells for storing data, the method comprising the following steps:

• a) fabricating a control memory array to have a reaction to voltage and temperature changes representative of a reaction of the memory storage cells to said voltage and said temperature changes;
• b) charging said control memory array;
• c) discharging said control memory array;
• d) generating a self-refresh cycle signal in response to said steps of charging and discharging;
• e) generating a self-refresh mode signal in response to said steps of charging and discharging;
• f) enabling the dynamic random access memory device for the refreshing in response to the self-refresh mode signal;
• and
• g) refreshing the memory storage cells in response to the self-refresh cycle signal.