Method of forming integrated limiter and amplifying devices

A method for making a limiter for an amplifier comprising providing a GaAs semi-insulating substrate, epitaxially growing an N.sub.B layer, an N+ doped layer, and an N doped layer on said substrate, etching said N doped layer, said N+ doped layer, and a portion of said N.sub.B layer to provide a mesa, depositing a first Ta layer, a first Au layer, and a second Ta layer on said substrate, including said mesa, for forming Schottky contacts with said N layer therebelow, locating areas on said mesa for Schottky diodes, etching said second Ta layer, said first Au layer, and said first Ta layer and leaving a portion of said first Ta layer and a portion of said first Au layer providing a first Schottky contact, and leaving another portion of said first Ta layer and another portion of said first Au layer providing a second Schottky contact, depositing a SiO.sub.2 layer and a Si.sub.3 N.sub.4 layer on said substrate, including said mesa and said Schottky contacts, applying masking material on said Si.sub.3 N.sub.4 layer, etching a first set of holes in said masking material, said Si.sub.3 N.sub.4 layer, and said SiO.sub.2 layer, leaving said masking material in place and electron beam depositing a GeAu layer and a second Au layer on said masking material and also in said first set of holes to yield a GeAu layer and an Au layer in a first hole of said first set, and a GeAu layer and an Au layer in a second hole of said first set, lifting off said masking material, said second Au layer, and said GeAu layer over said Si.sub.3 N.sub.4 layer, annealing and sinter alloying said Au layer and GeAu layer in said first hole, and said Au layer and said GeAu layer in said second hole to yield a first ohmic contact in said first hole, and a second ohmic contact in said second hole, etching a second set of holes in said Si.sub.3 N.sub.4 layer and said SiO.sub.2 layer to expose said Schottky contacts formed by said regions remaining from said first Ta layer and said first Au layer, depositing a series of layers comprising a third Ta layer, a third Au layer, a fourth Ta layer, a Ta.sub.2 O.sub.5 layer, a fifth Ta layer, and a fourth Au layer, on said substrate, including said mesa and including in said first set of holes, and said second set of holes over said Schottky contacts, etching said series of layers to form a capacitor provided by said Ta.sub.2 O.sub.5 layer between said fourth Ta layer and said fifth Ta layer, and to form an inductor provided by said third Ta layer and said third Au layer, and to form conductors provided by said third Ta layer and said third Au layer contacting said ohmic contacts and said Schottky contacts, such that said Schottky diodes form an anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor provided by said third Au layer and said third Ta layer on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference.

A method for making an MMIC, microwave and millimeter wave monolithic integrated circuit comprising providing a semi-insulating substrate, monolithically integrating an amplifier on said substrate, monolithically integrating a limiter on the same said substrate with said amplifier, and monolithically integrating a plurality of Schottky diodes on said substrate forming said limiter, said method comprising epitaxially growing a first set of one or more semiconductor layers, a stop etch layer, and a second set of one or more semiconductor layers on said substrate, etching said second set of one or more semiconductor layers to define a first section providing a Schottky diode array section, depositing a first set of one or more metal layers on said substrate, including said first section, forming Schottky contacts with one of said semiconductor layers of said second set therebelow, locating areas in said first section for Schottky diodes, etching said first set of one or metal layers and leaving metallization providing Schottky contacts at said areas, removing said stop etch layer outside said first section, etching said second set of one or more semiconductor layers to define a second section on said substrate having a mesa formed by said second set of one or more semiconductor layers and to define a mesa at said first section formed by said first set of one or more semiconductor layers and by said stop etch layer and by said second set of one or more semiconductor layers, depositing one or more insulating layers on said substrate, including said mesas at said first and second sections and said Schottky contacts, etching a first set of holes in said one or more insulating layers to expose said one or more semiconductor layers of said second set on said mesa of said first section, and etching a second set of holes in said one or more insulating layers to expose said one or more semiconductor layers of said first set on said mesa of said second section, depositing a second set of one or more metal layers in said first set of holes to form a first set of ohmic contacts with said second set of one or more semiconductor layers, and in said second set of holes to form a second set of ohmic contacts with said first set of one or more semiconductor layers, etching a third set of holes in said one or more insulating layers to expose said Schottky contacts, etching a gate hole in said one or more insulating layers to expose a portion of said first set of one or more semiconductor layers adjacent said second set of ohmic contacts, depositing gate metallization in said gate hole, depositing conductor metallization electrically contacting said first set of ohmic contacts, said second set of ohmic contacts, said Schottky contacts, and said gate metallization, such that said Schottky diodes form an anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, said conductor metallization on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output coupled to said gate metallization, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference.

A method for making an MMIC, microwave and millimeter wave monolithic integrated circuit comprising providing a GaAs semi-insulating substrate, epitaxially growing an N.sub.B layer, a first N doped layer, a first N+ doped layer, a AlGaAs layer, a second N+ doped layer, and a second N doped layer on said substrate, etching said second N doped layer and said second N+ doped layer, with said AlGaAs layer acting as a stop etch layer, depositing a first Ta layer, a first Au layer, and a second Ta layer on said second N doped layer for forming Schottky contacts, locating areas for Schottky diodes at a first section of said substrate, etching said second Ta layer, said first Au layer, and said first Ta layer and leaving a portion of said first Ta layer and a portion of said first Au layer providing a first Schottky contact, and leaving another portion of said first Ta layer and another portion of said first Au layer providing a second Schottky contact, removing said AlGaAs layer outside said first section, etching said first N+ doped layer and said first N doped layer to define a first mesa at said first section of said substrate and to define a second mesa at a second section of said substrate, depositing a SiO.sub.2 layer and a Si.sub.3 N.sub.4 layer on said substrate, including said first and second mesas and said Schottky contacts, applying photoresist on said Si.sub.3 N.sub.4 layer, etching a first set of holes in said photoresist, said Si.sub.3 N.sub.4 layer and said SiO.sub.2 layer on said first mesa, etching a second set of holes in said photoresist, said Si.sub.3 N.sub.4 layer, and said SiO.sub.2 layer on said second mesa, leaving said photoresist in place and electron beam depositing a GeAu layer and a second Au layer on said photoresist and also in said first and second sets of holes to yield a GeAu layer and an Au layer in the holes, lifting off said photoresist, said second Au layer, and said GeAu layer over said Si.sub.3 N.sub.4 layer, annealing and sinter alloying said Au layer and GeAu layer in said holes to yield first and second sets of ohmic contacts, etching a third set of holes in said Si.sub.3 N.sub.4 layer and said SiO.sub.2 layer to expose said Schottky contacts formed by said regions remaining from said first Ta layer and said first Au layer, applying masking material selected from the group consisting of PMMA and photoresist to said substrate, including said first and second mesas etching said masking material and said Si.sub.3 N.sub.4 layer and said SiO.sub.2 layer and a portion of said first N+ doped layer on said second mesa to provide a gate hole, depositing a Ti layer, a Pt layer, and a third Au layer on said substrate, including said masking material on said first and second mesas and in said gate hole, lifting off said third Au layer, said Pt layer, said Ti layer, and said masking material and leaving the portion of said Ti layer, said Pt layer, and said third Au layer in said gate hole as gate metallization, depositing a series of layers comprising a third Ta layer, a fourth Au layer, a fourth Ta layer, a Ta.sub.2 O.sub.5 oxide layer, a fifth Ta layer, and a fifth Au layer, on said substrate, including said first and second mesas and including in said first set of holes, said second set of holes, said third set of holes, and on said gate metallization, etching said series of layers to form a capacitor provided by said Ta.sub.2 O.sub.5 oxide layer between said fourth Ta layer and said fifth Ta layer, and to form an inductor provided by said third Ta layer and said fourth Au layer, and to form conductors provided by said third Ta layer and said fourth Au layer contacting said ohmic contacts and said Schottky contacts and said gate metallization, such that said Schottky diodes form an anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor provided by said fourth Au layer and said third Ta layer on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output coupled to said gate metallization, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference.