CMOS ESD protection structure

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• an n-channel MOS transistor composed of a source region and a drain region formed in said substrate and a gate electrode formed through a gate insulator on a surface of said substrate;
• a p-channel MOS transistor composed of a source region and a drain region formed in said substrate and a gate electrode formed through a gate insulator on said surface of said substrate, said p-channel MOS transistor constituting a CMOS inverter together with said n-channel MOS transistor;
• a first wiring layer electrically connected to said gate electrodes of said n-channel MOS transistor and said p-channel MOS transistor, a signal being supplied to said MOS transistor through said first wiring layer;
• a first interlayer insulator film having first contact holes arranged at intervals, said first interlayer insulator film being formed on said substrate and covering said source regions and said drain regions and said gate electrodes of said n-channel MOS transistor and said p-channel MOS transistor;
• a first contact layer and a second contact layer formed on said first interlayer insulator film, said first contact layer being selectively placed only over said source region, and said second contact layer being selectively placed only over said drain region of said n-channel MOS transistor;
• a second interlayer insulator film having second contact holes arranged between adjacent first contact holes, said second interlayer insulator film being formed on said first interlayer insulator film and covering said first contact layer and said second contact layer while keeping said first and second contact layers exposed through said second contact holes;
• a second wiring layer formed on said second interlayer insulator film, said second wiring layer being electrically connected to said source region of said p-channel MOS transistor;
• a third wiring layer formed on said second interlayer insulator film, said third wiring layer being electrically connected to said source region of said n-channel MOS transistor;
• and
• a fourth wiring layer formed on said second interlayer insulator film, said fourth wiring layer being electrically connected to said drain regions of said n-channel MOS transistor and said p-channel MOS transistor;
• wherein said first contact layer and said second contact layer are made of material higher in electric resistance than said second wiring layer, third wiring layer and fourth wiring layer;
• said source region and said drain region of said n-channel MOS transistor are electrically connected through said first contact holes to said first contact layer and said second contact layer, respectively;
• said first contact layer and said second contact layer are electrically connected through said second contact holes to said second wiring layer and said third wiring layer, respectively;
• said first interlayer insulator film and said second interlayer insulator film have third contact holes, said third contact holes passing through said first interlayer insulator film and said second interlayer insulator film;
• and
• said source region and said drain region of said p-channel MOS transistor are electrically connected through said third contact holes to said second wiring layer and said fourth wiring layer, respectively.