High speed counter for alternative up/down counting of pulse trains and method therefor

An asynchronous counter comprising:

• a plurality of flip-flops, cascade connected to one another, the plurality of flip-flops serially receiving successive pulse trains having varying numbers of pulses per pulse train;
• switching circuitry, coupled to the plurality of flip-flops, inverting the state of each flip-flop between a first set of pulse trains and a second set of pulse trains so that the counter computes a difference between the number of pulses of the first set of pulse trains and the number of pulses of the second set of pulses trains;
• and
• initialization circuitry, coupled to the plurality of flip-flops, initializing all of the flip-flops at each predetermined even number of pulse trains.

A method for computing a difference between pulses of successive pulse trains comprising the steps of:

• serially receiving successive pulse trains having varying number of pulses per pulse train;
• providing the pulse trains to a plurality of flip-flops that are cascade-connected to one another;
• inverting the state of each flip-flop between two successive pulse trains so that the counter computes a difference in the number of pulses of the successive pulse trains;
• and
• initializing each flip-flop at each predetermined even number of the pulse trains.