Fast programmable/resettable CMOS Johnson counters
AssigneeIntel Corporation
InventorKeng L. Wong
Life of this patent
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Abstract
An integrated circuit for frequency synthesis within a microprocessor. The integrated circuit includes at least one of n-bit Johnson counter being clocked by a clock internal to the microprocessor. The n-bit Johnson counter being coupled to odd-even logic which generates "2n-1" outputs having "even" and "odd" divide values. The odd-even logic is coupled to a multiplexor which is selected to pass a selected output to be fed back into the n-bit Johnson counter.
Claims36
A dividing circuit for frequency synthesis of an input clock signal having a preselected frequency to provide a divider output signal having a desired frequency, the dividing circuit comprising:
- counter means for generating a plurality of bit output signals in parallel, the counter means including a first plurality of flip-flops cascaded together, each output of the first plurality of flip-flops having a bit output signal line coupled thereto;
- resetting means for re-initializing the plurality of bit output signals;
- multiplexor means for selecting the divider output signal from the plurality of bit output signals;
- and
- feedback means for inputting the divider output signal into the counter means.
A dividing circuit for frequency synthesis of an input clock signal having a preselected frequency in order to provide a divider output signal having a desired frequency, the dividing circuit comprising:
- a multiple bit counter including a first plurality of cascaded flip-flops, wherein each output of the first plurality of cascaded flip-flops is separately coupled to a bit output signal line such that a plurality of bit output signals corresponding to the first plurality of cascaded flip-flops are outputted in parallel through the bit output signal lines,
- logic circuitry coupled to the first plurality of cascaded flip-flops through the bit output signal lines, wherein the logic circuitry generates a plurality of bit output signals which includes the corresponding plurality of bit output signals from the multiple bit counter and at least one bit output signal representing a frequency not harmonically related to any frequencies of the corresponding plurality of bit output signals if any one of the corresponding plurality of bit output signals is selected;
- a resetting mechanism for re-initializing the plurality of bit output signals;
- a multiplexor coupled to the logic circuitry through a plurality of signal lines corresponding to the plurality of bit output signals generated by the logic circuitry, the multiplexor being selected to transmit the divider output signal being one of the plurality of bit output signals;
- and
- a feedback signal line for inputting an inverted counter output signal into the multiple bit counter.
A dividing circuit for frequency synthesis of an input clock signal having a preselected frequency in order to obtain a divider output signal having a desired frequency, the dividing circuit comprising:
- counter means for generating a plurality of bit output signals, the counter means includes a plurality of cascaded bit slices clocked by the input clock signal, each of the plurality of cascaded bit slices includes
- means for latching information being inputted into a bit slice and for outputting the information through a bit output signal line,
- means for selectively driving the divider output signal having the desired frequency through a feedback circuit, and
- resetting means for re-initializing the bit slice.
A dividing circuit for frequency synthesis of an input clock signal having a preselected frequency in order to obtain a divider output signal having a desired frequency, the dividing circuit comprising:
- a first plurality of bit slices clocked by the input clock signal, the first plurality of bit slices are cascaded together through a second plurality of bit output signal lines where each of the second plurality of bit output signal lines couples an output of one bit slice to an input of an adjacent bit slice, the first plurality of bit slices further coupled together through a feedback circuit, wherein each of the first plurality of bit slices includes
- a master latch,
- a first slave latch coupled to the master latch through a primary signal line and one of the second plurality of bit output signal lines,
- a second slave latch coupled to the master latch through a parallel signal line and the feedback circuit, and
- a reset mechanism including a signal line coupled to a gate first transistor the primary signal line and the parallel signal line.
- a reset mechanism including
- a reset line,
- a first transistor, wherein a drain of the first transistor is coupled to the parallel signal line, a source of the first transistor coupled to ground and a gate of the first transistor coupled to the reset line, and
- a second transistor, wherein a source of the second transistor is coupled to the voltage supply, a drain of the second transistor is coupled to the primary signal line and a gate of the second transistor coupled to the reset line.
A computer system comprising:
- means for inputting information;
- means for storing the information;
- means for processing the information, the processing means, being able to perform frequency synthesis, includes
- means for providing dynamic feedback, the dynamic feedback means includes an internal oscillator generating an input clock signal having a preselected frequency;
- and
- means for dividing the input clock signal having a preselected frequency in order to provide a divider output signal having a desired frequency, said dividing means including
- counter means for generating a plurality of bit output signals in parallel;
- resetting means for re-initializing the plurality of bit output signals;
- multiplexor means for selecting one of the plurality of bit output signals;
- and
- feedback means for inputting the divider output signal into the counter means.
Dependencies are inferred from the claim text.