Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication

A method of controlling an integrated circuit fabrication process, comprising the steps of:

• (a) performing a first sequence of integrated circuit fabrication steps on a wafer comprising the steps of:
• forming and patterning a first set of one or more material layers on said wafer, wherein the first set of layers is deposited and patterned in such manner to create hills and valleys therein;
• forming a second set of one or more material layers over said first set of material layers;
• etching back the deposited second set of material layers to produce a surface on the resulting wafer;
• (b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of:
• scanning a predetermined area of said wafer's surface with an atomic force microscope;
• gathering surface height data from the atomic force microscope representing height with respect to position;
• generating from the gathered surface height data at least one signal indicative of surface planarity;
• comparing the at least one signal with predefined planarity criteria to determine if said etching back step produced a surface that meets said predefined planarity criteria.

A method of controlling an integrated circuit fabrication process, comprising the steps of:

• forming and patterning a first material layer on said wafer, wherein the first material layer is deposited and patterned in such manner to create hills and valleys therein;
• forming a second material layer over said first material layer;
• etching back the deposited second material layer to produce a surface on the resulting wafer;
• scanning a predetermined region of the wafer surface with an atomic force microscope;
• gathering data from the atomic force microscope representing height with respect to position;
• generating from the gathered data at least one signal indicative of surface roughness using a predetermined procedure;
• comparing the at least one signal indicative of surface roughness with predefined criteria;
• when the at least one signal is below a first predetermined threshold of the predetermined criteria, continuing with the integrated circuit fabrication process;
• when the at least one signal is within an intermediate range of said first predetermined threshold and a second predetermined threshold of the predetermined criteria, performing a remedial process on the wafer;
• and
• when the at least one signal is above said second predetermined threshold of the predetermined criteria, discarding the wafer.