US 5,420,447 AGranted

Double buffer base gate array cell

AssigneeSGS-Thomson Microelectronics S.A.

InventorCharles D. Waggoner

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Abstract

A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.

Claims18

Dependent claims

An integrated circuit, comprising a plurality of repetitively placed cells arranged in an array at a semiconducting surface of a body, each of said cells comprising:

a first active region of said semiconducting surface, having a first conductivity type and extending to first and second outer edge of the cell;
a second active region of said semiconducting surface, having a second conductivity type and extending to the first and second outer edges of the cell;
a first field oxide structure disposed at said semiconducting surface between said first and second active regions;
first and second outer electrodes extending across said first active region in a first direction, each of said first and second outer electrodes spaced away from the first and second outer edges, respectively, of the cell;
a first diffused region of said second conductivity type formed in said first active region and disposed between the first outer edge of the cell and said first outer electrode, so as to be in contact with a diffused region of said second conductivity type of an adjacent cell;
a second diffused region of said second conductivity type formed in said first active region and disposed between the second outer edge of the cell and said second outer electrode, so as to be in contact with a diffused region of said second conductivity type of an adjacent cell;
third and fourth outer electrodes extending across said second active region in said first direction, each of said third and fourth outer electrodes spaced away from first and second outer edges of the cell, respectively;
a third diffused region of said first conductivity type formed in said second active region between the first outer edge of the cell and said third outer electrode, so as to be in contact with a diffused region of said first conductivity type of an adjacent cell;
a fourth diffused region of said first conductivity type formed in said second active region between the second outer edge of the cell and said fourth outer electrode, so as to be in contact with a diffused region of said first conductivity type of an adjacent cell;
and
a first inner electrode extending across both said first and second active regions in said first direction, and disposed between said first and second outer electrodes in said first active region, and disposed between said third and fourth outer electrodes in said second active region.

8 more elements

An integrated circuit, comprising a plurality of repetitively placed cells arranged in an array at a semiconducting surface of a body at which complementary MOS circuits are realized, each of said cells comprising:

a plurality of p-type diffused regions disposed at said semiconducting surface;
a first outer electrode extending in a first direction between first and second ones of said plurality of p-type diffused regions, said first one of said plurality of p-type diffused regions extending to a first edge of said cell so as to be in physical contact with a p-type diffused region in an adjacent cell;
a second outer electrode extending in said first direction between third and fourth ones of said plurality of p-type diffused regions, said fourth one of said plurality of p-type diffused regions extending to a second edge of said cell;
a plurality of n-type diffused regions disposed at said semiconducting surface;
a third outer electrode extending in said first direction between first and second ones of said plurality of n-type diffused regions, said first one of said plurality of n-type diffused regions extending to the first edge of said cell so as to be in physical contact with an n-type diffused region in an adjacent cell;
a fourth outer electrode extending in said first direction between third and fourth ones of said plurality of n-type diffused regions, said fourth one of said plurality of n-type diffused regions extending to the second edge of said cell;
an inner field oxide structure disposed at said semiconducting surface between said pluralities of p-type and n-type diffused regions;
a first inner electrode extending in said first direction between said first and second outer electrodes, and between said third and fourth outer electrodes, said first inner electrode serving as a gate between a pair of said plurality of p-type diffused regions and as a gate between a pair of said plurality of n-type diffused regions.

5 more elements

Dependencies are inferred from the claim text.