Forming multi-layered interconnections with fluorine compound treatment permitting selective deposition of insulator

A method of manufacturing a semiconductor device, comprising the steps of:

• depositing a second silicon oxide film on a semiconductor substrate which has lower level wirings formed on a first silicon oxide film on said substrate;
• performing reactive ion etching using a fluorine compound gas to form a side wall consisting of said second silicon oxide film on said lower level wirings and at the same time to surface-treat said lower level wirings;
• selectively depositing a third silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases;
• depositing a fourth silicon oxide film on an entire surface of the semiconductor device and forming through-holes through said fourth silicon oxide film to said lower level wirings, forming conductive connections in said through-holes to said lower level wirings, and forming upper level wirings on said fourth silicon oxide film and connected to said conductive connections to connect to said lower level wirings.