Adaptive clock generation with pseudo random variation
AssigneeHewlett-Packard Company
InventorsSteve Kootstra, Daniel J. Powers
Life of this patent
Estimating the term…
Abstract
Adaptive clock generator including a master clock. A control means detects the current operating mode and, in response, provides a corresponding integer output N. A programmable pulse generator provides an output clock signal comprising a "high" pulse having a predetermined width followed by a "low" pulse having a width of N master clock periods. A dithered clock signal may be provided when the control means provides an integer output N selected from a set of integer values. Preferably, N is selected in a random or pseudo-random manner.
Claims4
A method in an adaptive clock generating system for providing an adaptive clock signal to a digital circuit having a processor and memory, said method comprising the steps of:
- initializing said adaptive clock signal to operate at a first clock frequency;
- determining that said processor is accessing said memory;
- decreasing said first clock frequency to a second clock frequency in response to said determining step;
- returning to said first clock frequency when said memory is no longer being accessed;
- detecting that said processor is processing an interrupt routine;
- increasing said first clock frequency to a third clock frequency in response to said detecting step;
- and
- returning to said first clock frequency when said interrupt routine has been processed.
An adaptive clock generating system for providing an adaptive clock signal to a digital circuit having a processor and memory, said system comprising:
- means for initializing said adaptive clock signal to operate at a first clock frequency;
- means for determining that said processor is accessing said memory;
- means for decreasing said first clock frequency to a second clock frequency in response to said determining means;
- means for returning to said first clock frequency when said memory is no longer being accessed;
- means for detecting that said processor is processing an interrupt routine;
- means for increasing said first clock frequency to a third clock frequency in response to said detecting step;
- and
- means for returning to said first clock frequency when said interrupt routine has been processed.
Dependencies are inferred from the claim text.