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AssigneeKabushiki Kaisha Toshiba
InventorsKohichi Takayama, Masanori Kinugasa, Munenobu Kida, Shuichi Shoji
Estimating the term…
At least one slit having a predetermined shape is formed around a contact region of a lower wiring layer formed on a substrate, and an insulating portion formed integrally with an insulating layer is embedded in this slit. This insulating layer is formed on the lower wiring layer and has a contact hole located at a position corresponding to the contact region. Since the insulating portion as a rectangular projecting portion projects into the slit downwardly from the rigid insulating layer, positional errors caused by thermal expansion of the lower wiring layer in annealing of the upper wiring layer can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained.
A semiconductor device having a multilayered wiring structure comprising:
A semiconductor device having a multilayered wiring structure comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Characterised by their conductive parts: layouts of interconnections
Characterised by their conductive parts: vias, e.g. via plugs
Generic packages, interconnections, connectors or other constructional details of devices covered by
Term ended 28 Mar 2012 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a multilayered wiring structure.
2. Description of the Related Art
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a sectional view showing a semiconductor device manufactured by conventional techniques;
FIG. 2A is a sectional view showing a semiconductor device according to the first embodiment of the present invention cut along the line II--II of FIG. 2B;
There will now be described an embodiment of this invention with reference to the accompanying drawings.
Semiconductor devices according to embodiments of the present invention will be described with reference to FIGS. 2A to 10. For illustrative convenience, each of the plan views of FIGS. 2B to 10 does not illustrate a substrate 5 and an insulating layer 7 but illustrates a structure cut along the line I--I of FIG. 2A.
FIGS. 2A and 2B are a sectional view and a plan view, respectively, showing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 2A, this semiconductor device comprises the insulating layer 7 formed on the semiconductor substrate 5, a lower wiring layer 1 formed on the insulating layer 7, an insulating layer 6 formed on the lower wiring layer 1 and having a contact hole 3 in a predetermined contact region, and made of a silicon oxide film (SiO.sub.2 film) or the like, and an upper wiring layer 2 formed on the insulating layer 6 and connected to the lower wiring layer 1 through the contact hole 3. Slits 4a and 4b are formed around the contact region of the lower wiring layer 1. Insulating portions 6a and 6b are embedded in the slits 4a and 4b and are formed integrally with the insulating layer 6. The insulating layer 6 has rigidity having a predetermined value or more. The "contact region" in the present invention is defined as a region which is located near the contact hole 3 and in contact with the upper wiring layer 2, or located near the upper wiring layer 2 and spaced apart from the contact hole 3 by a predetermined distance.