Semiconductor device having a basic cell region and an I/O cell region defined on a surface thereof

A semiconductor device comprising:

• a semiconductor chip having a basic cell region defined at the central area of a surface thereof;
• an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;
• a first insulating layer covering the semiconductor chip surface;
• first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;
• circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;
• a second insulating layer covering the first insulating layer and the first signal lines;
• a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region;
• and
• a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, wherein:
• each circuit element comprises an insulating-gate field-effect transistor;
• the input-output circuit cells comprise formed transistors;
• and
• the insulating-gate field-effect transistor has a larger channel length than a channel length of the formed transistors of the input-output circuit cells.

A semiconductor device comprising:

• a semiconductor chip having a basic cell region defined at the central area of a surface thereof;
• an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;
• a first insulating layer covering the semiconductor chip surface;
• first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;
• circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;
• a second insulating layer covering the first insulating layer and the first signal lines;
• a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region;
• and
• a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, two of the circuit elements, wherein
• each of two of the circuit elements is disposed at a respective corner adjacent to a common edge of the semiconductor chip surface;
• the two circuit elements and one of the associated terminals of the selected input-output circuit cell are interconnected by the second signal line;
• one of the two circuit elements is a resistor and the other one of the two circuit elements is a capacitor;
• and
• the input-output interface circuit has a CR time-constant determined based on the resistor and the capacitor.

A semiconductor device comprising:

• a semiconductor chip having a basic cell region defined at the central area of a surface thereof;
• an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;
• a first insulating layer covering the semiconductor chip surface;
• first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;
• circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;
• a second insulating layer covering the first insulating layer and the first signal lines;
• a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region;
• a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, wherein the circuit elements comprise a resistor and a capacitor connected in series and the input-output interface circuit has a CR time-constant determined by the resistor and the capacitor.