Self-cascoding CMOS device

A cascode transconductance circuit comprising:

• a first p-mos FET having a first gate, a first source, a first drain, and a first threshold voltage, said first drain connected to a first voltage;
• and
• a second p-mos FET having a second gate, a second drain, a second source, and a second threshold voltage, said second gate connected to said first gate of said first p-mos FET, said second source connected to a second voltage greater than said first voltage, said second drain connected to said first source of said first p-mos FET, and said second threshold voltage being at least 0.1 volts greater than said first threshold voltage to ensure that said second p-mos FET operates in its saturated region;
• wherein an input voltage applied to said connected together first and second gates of said first and second p-mos FETs, respectively, causes a proportional output current in response thereof at said second source of said second p-mos FET.

A cascode transconductance circuit constructed in a p- type substrate or well, comprising:

• a first gate electrode formed on a gate oxide layer over a surface of said p- type substrate or well;
• an n+ type drain region formed beneath said surface of said p- type substrate or well, and laterally extending towards a second edge from a first edge of said first gate electrode such that said n+ type drain region lies partially beneath said first gate electrode;
• a first n+ type source region formed beneath said surface of said p- type substrate or well, and laterally extending towards said first edge from said second edge of said first gate electrode such that said first n+ type source region lies partially beneath said first gate electrode;
• a first p type threshold adjust region formed adjacent to said first n+ type source region, and laterally extending from said first n+ type source region to a first point lying beneath said first gate electrode, said first point being at a first distance greater than zero from said first edge of said first gate electrode and a second distance greater than zero from said second edge of said first gate electrode;
• and
• a first region laterally extending from said n+ type drain region to said first p type threshold adjust region, wherein a first threshold voltage associated with said first gate electrode and said first p type threshold adjust region is at least 0.1 volts greater than a second threshold voltage associated with said first gate electrode and said first region.

A cascode transconductance circuit constructed in an n- type substrate or well, comprising:

• a first gate electrode formed on a gate oxide layer over a surface of said n- type substrate or well;
• a first p+ type source region formed beneath said surface of said n- type substrate or well, and laterally extending towards a second edge from a first edge of said first gate electrode such that said first p+ type source region lies partially beneath said first gate electrode;
• a p+ type drain region formed beneath said surface of said n- type substrate or well, and laterally extending towards said first edge from said second edge of said first gate electrode such that said p+ type drain region lies partially beneath said first gate electrode;
• a first p type threshold adjust region having a first concentration of p type dopants and formed adjacent to said first p+ type source region, and laterally extending from said p+ type source region to a first point lying beneath said first gate electrode, said first point being at a first distance greater than zero from said second edge of said first gate electrode and a second distance greater than zero from said first edge of said first gate electrode;
• and
• a second p type threshold adjust region having a second concentration of p type dopants and formed adjacent to said p+ type drain region, and laterally extending from said p+ type drain region to said first point lying beneath said first gate electrode, wherein said first and second concentrations of p type dopants are such that a second threshold voltage associated with said first gate electrode and said second p type threshold adjust region, is at least 0.1 volts greater than a first threshold voltage associated with said first gate electrode and said first p type threshold adjust region.