High voltage tolerant switch constructed for a low voltage CMOS process
AssigneeIntel Corporation
InventorsMichael J. Allen, Charles H. Lucas
Life of this patent
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Abstract
An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.
Claims10
A high voltage switching circuit for use in a low voltage integrated circuit comprising:
- a source voltage of a first level;
- first and second N well P channel field effect transistors each having source, drain, and gate terminals, the source and drain terminals of each of the first and second P channel field effect transistors being connected in series between the source of voltage of a first level and an output terminal;
- means for biasing the first and second P channel transistors whereby voltages less than breakdown voltages appear across junctions between P and N regions and oxide layers of such devices when switching voltages are applied to such transistors;
- means for providing an enabling voltage to one of the first and second P channel transistors;
- and,
- means for switching the other one of the first and second P channel transistors to a conducting condition.
An integrated circuit switch for switching voltages of a first high value in integrated circuits designed for processes utilizing lower source voltages, the switching circuit comprising:
- first and second integrated circuit field effect devices;
- each of the first and second devices being a P channel device having P+ source and drain areas deposited in a separate N- well of a P- substrate;
- each of the first and second devices having a gate area isolated from the N- well by a layer of oxide;
- each of the first and second devices including an N+ body area joined to the source area;
- the drain of the first device being connected to the source area of the second device;
- the source area of the first device being connected to a source of voltage of the first high value;
- the gate areas of each of the first and second devices being connected to receive enabling potential approximately one-half of the first high value;
- and,
- the drain of the second device being connected to an output terminal.
Dependencies are inferred from the claim text.