Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level

A semiconductor memory comprising a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of said plurality of transistors, a plurality of first level interconnection layers connected to other portions of said plurality of transistors, and a plurality of second level interconnection layers disposed above said stacked capacitors and said first level interconnection layers.

• each of said plurality of stacked capacitors comprising a first electrode layer, a capacitance insulating film formed on top of said first electrode layer, and a second electrode layer formed on top of said capacitance insulating film, said second electrode layer being connected to a portion of one of said plurality of second level interconnection layers.
• at least portions of said plurality of first level interconnection layers being connected to other portions of said plurality of second level interconnection layers.
• each of said plurality of first level interconnection layers sharing the same layer as at least one of said first electrode layer and said second electrode layer, and
• wherein each of said first level interconnection layers comprises a lower layer section formed from the same layer as that forming said first electrode layer, and an upper layer section formed over said lower layer section from the same layer as that forming said second electrode layer.