Method of routing three layer metal gate arrays using a channel router

Abstract

In a method for providing routing between logic cells, the logic cells are arranged in rows. Intercell connectors within each row of logic cells are aligned, for example in the middle of the rows, to form channel boundaries. The intercell connectors are then channel routed in metal layers above the logic cells. Alternately, intercell connectors are placed within the logic cells, however, these intercell connectors are not necessarily aligned. For each intercell connector which is not on a boundary of a routing channel, a substitute connector is located at the boundary of a routing channel. The substitute connectors and the intercell connectors which are on the boundaries of the routing channels are channel routed. Length of routing segments are then adjusted to substitute connectors to extend to intercell connectors instead of the substitute connectors.

Dependencies are inferred from the claim text.