Clock distribution method and apparatus for high speed circuits with low skew using counterpropaging true and complement re-generated clock signals with predetermined ramp shapes

A process for delivering high speed clock signals to circuits in an array comprised of a plurality of rows and columns of circuits while substantially reducing clock skew in delivering said clock signals to each circuit in said array, said array having first, second, third and fourth corners, and having a first clock bus having first and second conductors running between said first and second corners, and having a second clock bus having first and second conductors running between said third and fourth corners, and having a plurality of column clock buses each having first and second conductors associated with a particular column and each coupled to at least some of the circuits in said column, comprising:

• generating true and complement clock signals at said corners of said array from master true and complement clock signals such that a true clock signal is generated at said first corner of said array and a complement clock signal is generated at said second corner of said array, where said first and second corners of said array share a first edge thereof, and so that a true clock signal is generated at said third corner of said array and a complement clock is generated at said fourth corner of said array, where said third and fourth corners of said array share a second edge thereof opposite said first edge, and wherein said master clock signals must be delivered substantially simultaneously to each said corner of said array, each said true and complement differential clock signal generated at said first, second, third and fourth corners of said array having a ramp portion the duration of which exceeds the propagation delay experienced by a clock signal as it propagates along either said first or second clock bus;
• transmitting said true clock signal generated at said first corner of said array along said first conductor of said first clock bus toward said second corner, and simultaneously transmitting said complement clock signal generated at said second corner of said array along said second conductor of said first clock bus toward said first corner of said array;
• transmitting said true clock signal generated at said third corner of said array along said first conductor of second clock bus toward said fourth corner of said array, and simultaneously transmitting said complement clock signal generated at said fourth corner along said second conductor of said second clock bus toward said third corner of said array;
• receiving at the top of each column clock bus said true and complement clock signals counterpropagating along said first and second conductors of said first clock bus and regenerating therefrom on said first conductor of said column clock bus at the location of each said column a new true column clock signal each of which has a ramp portion the duration of which exceeds the propagation delay for a column clock signal to propagate down said column clock bus, said new true column clock signal commencing propagation down said first conductor of the corresponding column clock bus at the time when said true and complement clock signals on said first and second conductors of said first clock bus are substantially equal in amplitude at the position of the corresponding column;
• receiving at the bottom of each column clock bus said true and complement clock signals counterpropagating along said first and second conductors of said second clock bus and regenerating therefrom on said second conductor of said column clock bus at the location of each said column a new complement column clock signal which has a ramp portion the duration of which exceeds the propagation delay for a clock signal to propagate down said column clock bus, said complement column clock signal commencing propagation on said second conductor of the corresponding column clock bus in a direction opposite the direction of propagation of said true column clock signal at the time when said true and complement clock signals on said first and second conductors of said second clock bus are substantially equal in amplitude at the position of the corresponding column;
• and
• using the crossover point where the amplitudes of said true and complement column clock signals counterpropagating on said first and second conductors of said column clock buses are substantially equal as the clock marker for each said cell coupled to said column clock bus.

A process of transmitting high speed clock signals to all cells in an array comprised of a plurality of rows and columns of said cells of a field programmable integrated circuit such as a gate array while substantially eliminating clock skew, comprising:

• generating high speed true and complement differential, trapezoidal clock signals at each corner of said array, said true and complement differential, trapezoidal clock signals being generated simultaneously at each corner of said array by master clock generator and distributor circuits upon simultaneous arrival at each corner of said array of an externally generated master clock signal, each said true and complement differential, trapezoidal clock signal having a ramp portion the duration of which is longer than the propagation delay a true or complement differential, trapezoidal clock signal experiences traversing a clock bus running along an edge of said array orthogonal to the columns of said array, and transmitting the true differential trapezoidal clock signals from a first edge of the array parallel to said columns of said array to a second edge parallel to said first edge along first and second clock buses on opposite sides of said array, each of said first and second clock buses being oriented so as to be orthogonal to the columns thereof;
• receiving said high speed true and complement differential, trapezoidal clock signals at satellite clock receiver and distributor cells located at the top and bottom ends of a plurality of column clock buses and generating therefrom true and complement differential trapezoidal column clock signals at each of said top and bottom ends of each said column clock bus, each said true and complement differential, trapezoidal column clock signal having a ramp portion the duration of which exceeds the propagation delay experienced by a true or complement differential trapezoidal column clock signal propagating the length of a column of said array on a column clock bus each said true and complement differential, trapezoidal column clock signal pair corresponding to a particular column commencing propagation on the corresponding column clock bus at the time when said true and complement differential trapezoidal clock signals counterpropagating on said first and second clock buses are substantially equal in amplitude at the location of the corresponding column, and transmitting the true differential, trapezoidal column clock signals generated at the top of each column clock bus of the array to the bottom of said column clock bus along a conductor of said column clock bus designated to carry said true differential trapezoidal column clock signal for that column, and transmitting the complement differential, trapezoidal column clock signal generated at the bottom of each column up the corresponding column clock bus along a conductor of said column clock bus designated to carry said complement differential, trapezoidal column clock signal corresponding to said column to the top of the column;
• using the crossover point in amplitude between the true and complement differential trapezoidal column clock signals propagating on each column clock bus at the location of each cell as the clock marker for that cell.

An apparatus for distributing high speed clock signals on an integrated circuit comprised of an array of cells which can be interconnected with each other by a user in a programmable fashion, said array comprising a plurality of cells arranged into a plurality of rows and columns, comprising:

• first means for receiving a first pair of externally-generated, differential clock signals delivered simultaneously to each corner of said array and for simultaneously generating therefrom first and second differential clock signals which are to be counterpropagated across the top of said array in opposite directions along first and second conductors of a first bus which is parallel to the first row of said array, said first and second differential clock signals each having ramp portions which have a rise time which exceeds the propagation delay for a differential clock signal to traverse the array along said first bus, and for simultaneously generating from said first pair of externally-generated differential clock signals third and fourth differential clock signals which are to be counterpropagated across the bottom of said array in opposite directions along first and second conductors of a second bus which is parallel to the last row in said array, and for simultaneously transmitting said first and third differential clock signals from the upper and lower corners of the left side of said array, respectively, such that said first and third differential clock signals simultaneously propagate across said array from left to right on said first conductors of said first and second buses, respectively, and for simultaneously transmitting said second and fourth differential clock signals from the upper and lower corners on the right side of said array, respectively, such that said second and fourth differential clock signals simultaneously propagate on said second conductors of said first and second buses, respectively, across said array from right to left whereby the direction of propagation of said second and fourth differential clock signals is opposite the direction of propagation of said first and third differential clock signals, said transmitting of said second and fourth differential clock signals being simultaneous with the transmitting of said first and third differential clock signals;
• and
• second means for generating on a column clock bus corresponding to each said column of said array differential column clock signals having ramp portions with rise times which exceed the propagation delay of said column clock buses at a predetermined time for each said column, and for counterpropagating said differential column clock signals in opposite directions along each said column clock bus in said array at said predetermined time for each said column, said predetermined time being determined for each column as the time when said first, second, third and fourth differential clock signals counterpropagating on said first bus and second bus have equal amplitudes at the position of said column, each said column clock bus including first and second electrically isolated conductors, said second means including a plurality of top secondary clock receiver and distributor circuits, one for each column and located at the top of each said column clock bus each said top secondary clock receiver and distributor circuit coupled to at least said first conductor of the corresponding said column clock bus, said top secondary clock receiver and distributor circuits being coupled to said first and second conductors of said first bus so as to receive said first and second differential clock signals transmitted by said first means from the upper right and left corners of said array and generating therefrom at the top of each column a first differential column clock signal at said predetermined time for each said column and propagating on said first conductor of the corresponding clock bus, said second means further including a plurality of bottom secondary clock receiver and distributor cells, one for each column and located at the bottom of the corresponding column clock bus, each said bottom secondary clock receiver and distributor cell coupled to said first and second conductors of the corresponding column clock bus and each coupled to said first and second conductors of said second bus so as to receive said third and fourth differential clock signals counterpropagating thereon and transmitted from said first means from the lower left and right corners of said array, each said bottom secondary clock receiver and distributor circuit for generating from said third and fourth differential clock signals counterpropagating on said second bus a second differential column clock signal at the bottom of each column clock bus, each of said first, and second, differential column clock signals having ramp portions with rise times which exceed the propagation delay of a differential column clock signal propagating down a column clock bus of said array, each said secondary clock receiver and distributor circuit at any particular column generating said first and second differential column clock signals at said predetermined time for that column, said second differential column clock signal being symmetrical and differential with said first differential column clock signal, each said top secondary clock receiver and distributor circuit being structured and coupled to said first bus and said column clock bus for the corresponding column so as to transmit said first differential column clock signal down the first conductor of the associated column clock bus at the predetermined time for said column, and each said bottom secondary clock receiver and distributor circuit for transmitting said second differential column clock signal simultaneously with the transmission of said first differential column clock signal for the corresponding column, said second differential column clock signal being transmitted in a direction on the corresponding column clock bus so as to counterpropagate up the associated column clock bus on a second conductor of the corresponding said column clock bus.

An apparatus for distributing high speed clock signals on an integrated circuit comprised of an array of cells which can be interconnected with each other by a user in a programmable fashion, said array comprising a plurality of cells arranged into a plurality of rows and columns, each column having a column clock bus comprised of first and second conductors associated therewith, said array also having a first bus comprised of first and second conductors running parallel to the top row of said array and a second bus comprised of first and second conductors running parallel to the bottom row of said array, comprising:

• first means for receiving a first pair of externally generated differential clock signals generated outside said integrated circuit and delivered simultaneously to each corner of said array and for generating therefrom first and second complementary differential clock signals having ramp portions each of which has a rise time which exceeds the propagation delay for a differential clock signal to propagate across the array on said first bus, and for simultaneously transmitting said first and second complementary differential clock signals from opposite ends of said first bus such said the true and complement differential clock signals counterpropagate in opposite directions on said first and second conductors of said first bus, said counterpropagation starting simultaneously at the time when the amplitudes of said first pair of externally generated differential clock signals are equal and for generating from said first pair of external differential clock signals third and fourth complementary differential clock signals having ramp portions each of which has a rise time which exceeds the propagation delay for a differential clock signal to propagate across the array on said second bus, and for simultaneously transmitting said third and fourth complementary differential clock signals from opposite ends of said second bus such that said third and fourth differential clock signals counterpropagate in opposite directions on said first and second conductors of said second bus, said counterpropagation starting simultaneously at the time when the amplitudes of said first pair of external differential clock signals are equal and simultaneously with the transmission of said first and second complementary differential clock signals on said first bus;
• and
• second means coupled to the bottom and top of each column clock bus, for generating true and complement differential column clock signals at the top of each column clock bus from said first and second complementary differential clock signals counterpropagating on said first bus, and for generating true and complement differential clock signals at the bottom of each column clock bus from said third and fourth complementary differential clock signals counterpropagating on said second bus, and, at the time the amplitudes of said first and second complementary differential clock signals are equal at the top of each column, transmitting said true differential column clock signal generated at the top of the corresponding column down the corresponding column clock bus, and, at the time the amplitudes of said third and fourth complementary differential clock signals are equal at the bottom of each column, transmitting said complementary differential column clock signal generated at the bottom of the corresponding column so as to propagate up the corresponding clock bus thereby creating simultaneously transmitted, complementary differential column clock signals counterpropagating on each column clock bus, each of said true and complement differential column clock signals generated at the top and bottom of each said column clock bus having ramp portions with rise times which exceed the propagation delay of a differential clock signal propagating down said column clock bus such the time at the location of each cell when the amplitudes are equal of the counterpropagating complementary differential column clock signals serves as a clock marker which substantially eliminates clock skew.

A clock pulse distribution apparatus for a circuit comprised of a plurality of cells arranged into a rectangular array comprising at least two rows and at least two columns, comprising:

• a plurality of input ports located at the corners of said array for simultaneously receiving master clock signals from a master clock;
• a first master clock bus having first and second conductors running along a first edge of said array;
• a second master clock bus having first and second conductors running along a second edge of said array which is parallel to and opposite said first edge;
• first master clock generation means coupled to one of said plurality of input ports and to a first conductor at a first end of said first master clock bus, for receiving a said master clock signals and outputting on said first conductor a true clock pulse having a rise time which is longer than the time it takes said true clock pulse to propagate along said first edge of said array on said first conductor;
• second master clock generation means coupled to a different one of said plurality of input ports than said first master clock generation means and to a second conductor of said first master clock bus at the end of said first master clock bus which is opposite said first end, for receiving said master clock signals and outputting on said second conductor a complementary clock pulse having a rise time which is longer than the time it takes said clock pulse to propagate along said first edge of said array on said second conductor and which is substantially identical to the rise time of said true clock pulse;
• third master clock generation means coupled to a different one of said plurality of input ports than said first and second master clock generation means and to a first conductor at a first end of said second master clock bus, for receiving said master clock signals and outputting on said first conductor a true clock pulse having a rise time which is longer than the time it takes said true clock pulse to propagate along said second edge of said array on said first conductor;
• fourth master clock generation means coupled to a different one of said plurality of input ports than said first, second and third master clock generation means and to a second conductor of said second master clock bus at the end of said second master clock bus which is opposite said first end, for receiving said master clock signals and outputting on said second conductor a complementary clock pulse having a rise time which is longer than the time it takes said complementary clock pulse to propagate along said first edge of said array on said second conductor and which is substantially identical to the rise time of said true clock pulse;
• and for each column of said array:
• a first column clock driver means coupled to said first and second conductors of said first master clock bus and to each cell in said column, for outputting a true clock column pulse at the time when said true and complementary clock signals output by said first and second master clock generation means are equal in amplitude at the location of said column, said true clock column pulse having a rise time longer than the propagation delay for said true clock column pulse to propagate to all cells in said column;
• a second column clock driver means coupled to said first and second conductors of said second master clock bus and to each cell in said column, for outputting a complementary clock column pulse at the time when said true and complementary clock signals output by said third and fourth master clock generation means are equal in amplitude at the location of said column, said complementary clock column pulse having a rise time longer than the propagation delay for said complementary clock column pulse to propagate to all cells in said column and which is substantially
• equal to the rise time of said true clock column pulse;
• and wherein the clock arrival time for any particular cell of said array is the time when the amplitudes of the true and complementary clock column pulses which are counterpropagating along each column are equal in amplitude at the location of the particular cell.