Gate array integrated semiconductor device having stabilized power supply potentials

A gate array integrated semiconductor device comprising;

• a first power supply connection for receiving a first potential;
• a second power supply connection for receiving a second potential which is higher than the first potential;
• and
• at least one unused unit cell of a P-channel MOS transistor type, whose transistors are never operated, each unused unit cell including an N-type semiconductor region connected to said second power supply connection and P-type semiconductor regions connected to said first power supply connection, said P-type semiconductor regions being formed within said N-type semiconductor region, thereby reversely-biasing said N-type and P-type semiconductor regions.

A gate array integrated semiconductor device comprising;

• a first power supply connection for receiving a first potential;
• a second power supply connection for receiving a second potential which is higher that the first potential;
• and
• at least one unused unit cell of a N-channel MOS transistor type, whose transistors are never operated, each unused unit cell including a P-type semiconductor region connected to said first power supply connection and N-type semiconductor regions connected to said second power supply connection, said N-type semiconductor regions being formed within said P-type semiconductor regions, thereby reversely-biasing said P-type and N-type semiconductor regions.

A gate array integrated semiconductor device comprising:

• a first power supply connection for receiving a first potential;
• a second power supply connection for receiving a second potential which is higher than the first potential;
• and
• at least one unused unit cell of an NPN bipolar transistor type, whose transistors are never operated, each unused unit cell including a P-type semiconductor region connected to said first power supply connection and two N-type semiconductor regions sandwiching said P-type semiconductor region, one of said N-type semiconductor regions being connected to said second power supply connection, thereby reversely-biasing said N-type semiconductor region and said P-type semiconductor region.

A gate array integrated semiconductor device comprising;

• a first power supply connection for receiving a first potential;
• a second power supply connection for receiving a second potential which is higher than the first potential;
• and
• at least one unused unit cell of a PNP bipolar transistor type, whose transistors are never operated, each unused unit cell including a N-type semiconductor region connected to said second power supply connection and two P-type semiconductor regions sandwiching said N-type semiconductor region, one of said P-type semiconductor regions being connected to said first power supply connection, thereby reversely-biasing said P-type semiconductor region and said N-type semiconductor region.